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ARM FastModels for TrustZone Development

Earlence Fernandes
Note: This was originally posted on 22nd August 2013 at http://forums.arm.com

I am trying to learn about TrustZone and I've downloaded the FastModels 8.1 simulator.
The license I can obtain is only for the Cortex A8 Eval Board, and The ref manual for FastModels implies that
no trust zone is built in.

Which fast model I can use to experiment with trust zone?
How do I get the required evaluation license? I am a student and have a .edu email address?
Anyone else with similar experience? My first step is to boot a linux kernel in secure world.

-Earlence
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  • Arm Employee Badge
    Note: This was originally posted on 27th August 2013 at http://forums.arm.com


    Ok, So I;ve been looking at the VE Cortex A9 LISA files for the daughterboard and I see the following lines:

    securitydecoder.pvbus_m_range[ 0x0000000000..0x0007FFFFFF ] => secure_region.pvbus_input   [ 0x0000000000..0x0007FFFFFF ];
            securitydecoder.pvbus_m_range[ 0x0008000000..0x007DFFFFFF ] => nonsecure_region.pvbus_input[ 0x0008000000..0x007DFFFFFF ];
            securitydecoder.pvbus_m_range[ 0x007E000000..0x007FFFFFFF ] => secure_region.pvbus_input   [ 0x007E000000..0x007FFFFFFF ];
            securitydecoder.pvbus_m_range[ 0x0080000000..0xFFFFFFFFFF ] => nonsecure_region.pvbus_input[ 0x0080000000..0xFFFFFFFFFF ];

    So there are 2 secure and 2 nonsecure regions?

    Also the following lines:
    securepvbusdecoder.pvbus_m_range[0x0004000000..0x000401FFFF] => secureSRAM.pvbus; // 128kB Secure SRAM
            securepvbusdecoder.pvbus_m_range[0x007E000000..0x007FFFFFFF] => secureDRAM.pvbus; //  32MB Secure DRAM

    So I'm guessing that these are the physical address ranges for secure static and secure dynamic RAM?

    How does it relate to the regions defined above?

    -Earlence


    You have to understand that these are part of a decode chain.

    The CPU PVBus feeds into the securitydecoder (which is just a  PVBus decoder) which splits accesses into 2 pairs of ranges - each pair of secure/nonsecure ranges handled by a TZSwitch.
    The two TZSwitches (called nonsecure_region and secure_region) then pass on - in partial crossover wiring - to two ordinary PVBus decoders (one secure and one non-secure) that handle a whole set of ranges for the secure and  non secure mem and peripherals.

    This arrangement is to emulate the actual specified wiring in a Versatile Express.

    The PVBus Decoder is just a static address mapping component.

    And yes - all addresses are Physical Addresses.

    Does this clarify matters?

    Chris
Reply
  • Arm Employee Badge
    Note: This was originally posted on 27th August 2013 at http://forums.arm.com


    Ok, So I;ve been looking at the VE Cortex A9 LISA files for the daughterboard and I see the following lines:

    securitydecoder.pvbus_m_range[ 0x0000000000..0x0007FFFFFF ] => secure_region.pvbus_input   [ 0x0000000000..0x0007FFFFFF ];
            securitydecoder.pvbus_m_range[ 0x0008000000..0x007DFFFFFF ] => nonsecure_region.pvbus_input[ 0x0008000000..0x007DFFFFFF ];
            securitydecoder.pvbus_m_range[ 0x007E000000..0x007FFFFFFF ] => secure_region.pvbus_input   [ 0x007E000000..0x007FFFFFFF ];
            securitydecoder.pvbus_m_range[ 0x0080000000..0xFFFFFFFFFF ] => nonsecure_region.pvbus_input[ 0x0080000000..0xFFFFFFFFFF ];

    So there are 2 secure and 2 nonsecure regions?

    Also the following lines:
    securepvbusdecoder.pvbus_m_range[0x0004000000..0x000401FFFF] => secureSRAM.pvbus; // 128kB Secure SRAM
            securepvbusdecoder.pvbus_m_range[0x007E000000..0x007FFFFFFF] => secureDRAM.pvbus; //  32MB Secure DRAM

    So I'm guessing that these are the physical address ranges for secure static and secure dynamic RAM?

    How does it relate to the regions defined above?

    -Earlence


    You have to understand that these are part of a decode chain.

    The CPU PVBus feeds into the securitydecoder (which is just a  PVBus decoder) which splits accesses into 2 pairs of ranges - each pair of secure/nonsecure ranges handled by a TZSwitch.
    The two TZSwitches (called nonsecure_region and secure_region) then pass on - in partial crossover wiring - to two ordinary PVBus decoders (one secure and one non-secure) that handle a whole set of ranges for the secure and  non secure mem and peripherals.

    This arrangement is to emulate the actual specified wiring in a Versatile Express.

    The PVBus Decoder is just a static address mapping component.

    And yes - all addresses are Physical Addresses.

    Does this clarify matters?

    Chris
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