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Performance Counters on ARM1176JZF-S

Note: This was originally posted on 14th August 2013 at http://forums.arm.com

Hi,

I have a question about the performance counters on an ARM1176JZF-S. Does the event 0xB count L1 or L2 data cache misses?

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Martin Weidmann over 12 years ago

Note: This was originally posted on 19th August 2013 at http://forums.arm.com

Couple of thoughts...

You running bare-metal? As you can't typically access the PMU directly from user space under Linux.

You should probably make "c" and/or a volatile, even at a low optimization level the compiler might eliminate your code otherwise.

I'd suggest taking a look at the assembler code the compiler has generated, to make sure it's what you expected.
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Martin Weidmann over 12 years ago

Note: This was originally posted on 19th August 2013 at http://forums.arm.com

Couple of thoughts...

You running bare-metal? As you can't typically access the PMU directly from user space under Linux.

You should probably make "c" and/or a volatile, even at a low optimization level the compiler might eliminate your code otherwise.

I'd suggest taking a look at the assembler code the compiler has generated, to make sure it's what you expected.
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