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Performance Counters on ARM1176JZF-S

Andreas Abel
Note: This was originally posted on 14th August 2013 at http://forums.arm.com

Hi,

I have a question about the performance counters on an ARM1176JZF-S. Does the event 0xB count L1 or L2 data cache misses?
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  • Arm Employee Badge
    Note: This was originally posted on 15th August 2013 at http://forums.arm.com

    The ARM1176JZ(F)-S doesn't have a built-in L2 cache.  So any cache related stats from the processor's PMU will be about the L1 caches.

    It's quite possible there's a non-integrated L2 cache (I'm guessing your using a Raspberry Pi, but I'm afraid I don't know whether the chip on that board does/doesn't have one).  If it is present, it might have it's performance counters.
Reply
  • Arm Employee Badge
    Note: This was originally posted on 15th August 2013 at http://forums.arm.com

    The ARM1176JZ(F)-S doesn't have a built-in L2 cache.  So any cache related stats from the processor's PMU will be about the L1 caches.

    It's quite possible there's a non-integrated L2 cache (I'm guessing your using a Raspberry Pi, but I'm afraid I don't know whether the chip on that board does/doesn't have one).  If it is present, it might have it's performance counters.
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