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Performance Counters on ARM1176JZF-S

Andreas Abel
Note: This was originally posted on 14th August 2013 at http://forums.arm.com

Hi,

I have a question about the performance counters on an ARM1176JZF-S. Does the event 0xB count L1 or L2 data cache misses?
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  • Arm Employee Badge
    Note: This was originally posted on 20th August 2013 at http://forums.arm.com

    If you are running Linux or some other "big OS" then it is likely that your application is getting interrupted while it is running (timer threads, interrupts, background processes, etc). The counters are global to the core so you may well find random "other stuff" runs between your counter reset and the counter sampling if you were pre-empted between the two.

    Some of the newer kernels include support for hardware counters in the perf infrastructure, and that can include support for context switching the counters when processes change.

    Secondly, it is always worth double checking the disassembly to check the instruction ordering is looking sensible too. The "volatile" part in "asm volatile" ensures the compiler doesn't optimize it out, but doesn't provide any kind of compiler barrier / memory barrier semantics so the compiler might reorder instructions. With -O0 it is unlikely, but always worth checking. Sticking "memory" in the register clobber list should stop that happening.
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  • Arm Employee Badge
    Note: This was originally posted on 20th August 2013 at http://forums.arm.com

    If you are running Linux or some other "big OS" then it is likely that your application is getting interrupted while it is running (timer threads, interrupts, background processes, etc). The counters are global to the core so you may well find random "other stuff" runs between your counter reset and the counter sampling if you were pre-empted between the two.

    Some of the newer kernels include support for hardware counters in the perf infrastructure, and that can include support for context switching the counters when processes change.

    Secondly, it is always worth double checking the disassembly to check the instruction ordering is looking sensible too. The "volatile" part in "asm volatile" ensures the compiler doesn't optimize it out, but doesn't provide any kind of compiler barrier / memory barrier semantics so the compiler might reorder instructions. With -O0 it is unlikely, but always worth checking. Sticking "memory" in the register clobber list should stop that happening.
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