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Performance Counters on ARM1176JZF-S

Andreas Abel
Note: This was originally posted on 14th August 2013 at http://forums.arm.com

Hi,

I have a question about the performance counters on an ARM1176JZF-S. Does the event 0xB count L1 or L2 data cache misses?
Parents
  • Note: This was originally posted on 19th August 2013 at http://forums.arm.com


    You running bare-metal?  As you can't typically access the PMU directly from user space under Linux.

    It is possible to access the PMU directly from user space if a specific bit in the "Secure User and Non-secure Access Validation Control Register" is set in kernel mode (see http://sandsoftwares...ent-and-tuning/).


    You should probably make "c" and/or a volatile, even at a low optimization level the compiler might eliminate your code otherwise.

    I just tried that, but it didn't make a difference. Also, the last statement "printf("%d\n",c);" should prevent a and c from being eliminated.
Reply
  • Note: This was originally posted on 19th August 2013 at http://forums.arm.com


    You running bare-metal?  As you can't typically access the PMU directly from user space under Linux.

    It is possible to access the PMU directly from user space if a specific bit in the "Secure User and Non-secure Access Validation Control Register" is set in kernel mode (see http://sandsoftwares...ent-and-tuning/).


    You should probably make "c" and/or a volatile, even at a low optimization level the compiler might eliminate your code otherwise.

    I just tried that, but it didn't make a difference. Also, the last statement "printf("%d\n",c);" should prevent a and c from being eliminated.
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