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Semihosting with Cortex-A5 and T32

Paras (O) Agarwal
Note: This was originally posted on 9th August 2013 at http://forums.arm.com

With Semihosting enabled, after seeing SVC 0xAB (for SYS_WRITE; R0=5) by Cortex-A5, how the message is passed to the DAP/debugger? In the code, I'm not handling SVC exception. Even I'm not able to do a 'vector catch' here.

Prints are coming on T32.
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  • Note: This was originally posted on 12th August 2013 at http://forums.arm.com


    With Semihosting enabled, after seeing SVC 0xAB (for SYS_WRITE; R0=5) by Cortex-A5, how the message is passed to the DAP/debugger? In the code, I'm not handling SVC exception. Even I'm not able to do a 'vector catch' here.

    Prints are coming on T32.



    Please go through the following link. it might help you to understand semihosting operations
    http://infocenter.arm.com/help/topic/com.arm.doc.dui0471i/DUI0471I_developing_for_arm_processors.pdf
    The function angel_SWIreason_EnterSVC Sets the processor to Supervisor mode and disables all interrupts by setting both interrupt mask
    bits in the new CPSR.
    SVC 0xAB In ARM state and Thumb state, excluding ARMv6-M and ARMv7-M. This
    behavior is not guaranteed on all debug targets from ARM or from third parties. I am not sure if it is debug hardware (Trace 32, DSTREAM) dependent.
    The SVC number indicates to the debug agent that the SVC instruction is a semihosting request

Reply
  • Note: This was originally posted on 12th August 2013 at http://forums.arm.com


    With Semihosting enabled, after seeing SVC 0xAB (for SYS_WRITE; R0=5) by Cortex-A5, how the message is passed to the DAP/debugger? In the code, I'm not handling SVC exception. Even I'm not able to do a 'vector catch' here.

    Prints are coming on T32.



    Please go through the following link. it might help you to understand semihosting operations
    http://infocenter.arm.com/help/topic/com.arm.doc.dui0471i/DUI0471I_developing_for_arm_processors.pdf
    The function angel_SWIreason_EnterSVC Sets the processor to Supervisor mode and disables all interrupts by setting both interrupt mask
    bits in the new CPSR.
    SVC 0xAB In ARM state and Thumb state, excluding ARMv6-M and ARMv7-M. This
    behavior is not guaranteed on all debug targets from ARM or from third parties. I am not sure if it is debug hardware (Trace 32, DSTREAM) dependent.
    The SVC number indicates to the debug agent that the SVC instruction is a semihosting request

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