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Semihosting with Cortex-A5 and T32

Note: This was originally posted on 9th August 2013 at http://forums.arm.com

With Semihosting enabled, after seeing SVC 0xAB (for SYS_WRITE; R0=5) by Cortex-A5, how the message is passed to the DAP/debugger? In the code, I'm not handling SVC exception. Even I'm not able to do a 'vector catch' here.

Prints are coming on T32.
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  • Note: This was originally posted on 12th August 2013 at http://forums.arm.com


    With Semihosting enabled, after seeing SVC 0xAB (for SYS_WRITE; R0=5) by Cortex-A5, how the message is passed to the DAP/debugger? In the code, I'm not handling SVC exception. Even I'm not able to do a 'vector catch' here.

    Prints are coming on T32.


    Can you explain more about what you are trying to do, what you want to happen and what is happening?  In particular I can't tell if you are having trouble with a different debugger (if so which one) or when using no debugger.

    When a debugger that does semihosting is attached (and correctly configured) it will place a vector catch or breakpoint on the SVC vector.  When the target does a semihosting operation the debugger will stop the target, do the operation and resume the target.
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  • Note: This was originally posted on 12th August 2013 at http://forums.arm.com


    With Semihosting enabled, after seeing SVC 0xAB (for SYS_WRITE; R0=5) by Cortex-A5, how the message is passed to the DAP/debugger? In the code, I'm not handling SVC exception. Even I'm not able to do a 'vector catch' here.

    Prints are coming on T32.


    Can you explain more about what you are trying to do, what you want to happen and what is happening?  In particular I can't tell if you are having trouble with a different debugger (if so which one) or when using no debugger.

    When a debugger that does semihosting is attached (and correctly configured) it will place a vector catch or breakpoint on the SVC vector.  When the target does a semihosting operation the debugger will stop the target, do the operation and resume the target.
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