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Semihosting with Cortex-A5 and T32

Paras (O) Agarwal
Note: This was originally posted on 9th August 2013 at http://forums.arm.com

With Semihosting enabled, after seeing SVC 0xAB (for SYS_WRITE; R0=5) by Cortex-A5, how the message is passed to the DAP/debugger? In the code, I'm not handling SVC exception. Even I'm not able to do a 'vector catch' here.

Prints are coming on T32.
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  • Arm Employee Badge
    Note: This was originally posted on 13th August 2013 at http://forums.arm.com

    I don't know the details, but there's no need for library code to write DBGDTRTX.  When the target stops on the vector catch/breakpoint the debugger can determine that it has stopped because of a semihosting SVC and then read/write the registers and memory in the usual debugger way.  Then the debugger can simulate returning from the SVC and resume the target.
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  • Arm Employee Badge
    Note: This was originally posted on 13th August 2013 at http://forums.arm.com

    I don't know the details, but there's no need for library code to write DBGDTRTX.  When the target stops on the vector catch/breakpoint the debugger can determine that it has stopped because of a semihosting SVC and then read/write the registers and memory in the usual debugger way.  Then the debugger can simulate returning from the SVC and resume the target.
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