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Semihosting with Cortex-A5 and T32

Note: This was originally posted on 9th August 2013 at http://forums.arm.com

With Semihosting enabled, after seeing SVC 0xAB (for SYS_WRITE; R0=5) by Cortex-A5, how the message is passed to the DAP/debugger? In the code, I'm not handling SVC exception. Even I'm not able to do a 'vector catch' here.

Prints are coming on T32.

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Martin Weidmann over 12 years ago

Note: This was originally posted on 12th August 2013 at http://forums.arm.com

Broadly - yes.

The debugger also has to perform a pseudo exception return at the end, as the application is not expected to handle the SVC.
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Martin Weidmann over 12 years ago

Note: This was originally posted on 12th August 2013 at http://forums.arm.com

Broadly - yes.

The debugger also has to perform a pseudo exception return at the end, as the application is not expected to handle the SVC.
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