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TrustZone MMU Validation

Scott Cloutier
Note: This was originally posted on 19th July 2013 at http://forums.arm.com

I am running code in Secure Mode on a Cortex-A9 platform.  The MMU registers within the CP15 are bank switched when secure mode is entered.  Is it possible to read READ the normal world TTBR0/1 and TTBCR registers.  What is involved in doing this?

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  • Arm Employee Badge
    Note: This was originally posted on 19th July 2013 at http://forums.arm.com

    Switch into monitor mode
    Disable interrupts,
    Write NS=1 into the CP15 operation to access the normal world copy of the banked registers
    Read values from TTBR/TTBCR into registers
    Set NS=0, re-enable interrupts
    Return out of monitor mode.

    Basically you need NS=1 to access the banked state, and the only place you can do this without changing into the Normal world execution is in monitor mode. The rest of the faffing about with interrupts is just to make this safe.

    HTH,
    Iso
Reply
  • Arm Employee Badge
    Note: This was originally posted on 19th July 2013 at http://forums.arm.com

    Switch into monitor mode
    Disable interrupts,
    Write NS=1 into the CP15 operation to access the normal world copy of the banked registers
    Read values from TTBR/TTBCR into registers
    Set NS=0, re-enable interrupts
    Return out of monitor mode.

    Basically you need NS=1 to access the banked state, and the only place you can do this without changing into the Normal world execution is in monitor mode. The rest of the faffing about with interrupts is just to make this safe.

    HTH,
    Iso
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