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Cortex-a7 dual-issue ?

ray song
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  • Note: This was originally posted on 21st May 2013 at http://forums.arm.com


    Non-symmetric means that the two pipelines support different operations.

    I don't have a Cortex-A7 so I can't test it directly, and ARM's TRM documents don't give any information on instruction timing anymore.. but GCC source has some information:

    https://github.com/m...onfig/arm/arm.c

    If I'm reading this right it means that Cortex-A7 is dual issue (should mean it decodes two instructions per cycle) and can execute simple ALU/move and branch/call instructions in the dual issue pipeline. However, according to the pipeline description file here:

    https://github.com/m...rm/cortex-a7.md

    It would seem that only ALU instructions with immediate operands can dual issue.

    If you ran a test that showed dual issue didn't work can you show what you did?



    Thanks Exophase,

    I update my code and test again. "It would seem that only ALU instructions with immediate operands can dual issue." you are right.
    cortex-A7 can dual-issue is limited. ARM pipeline can dual issue with the "dual issue pipe"but  ALU instructions with immediate operands  can't dual issue with the neon/floating-pipe.
    The A31 neon ALU performance is the same as the Cortex-a5's,But the Cortex-a7 core really has 64-bit load/store path.
    Cortex-A5 only has 32-bit load/store path.

    Thank you once more!
Reply
  • Note: This was originally posted on 21st May 2013 at http://forums.arm.com


    Non-symmetric means that the two pipelines support different operations.

    I don't have a Cortex-A7 so I can't test it directly, and ARM's TRM documents don't give any information on instruction timing anymore.. but GCC source has some information:

    https://github.com/m...onfig/arm/arm.c

    If I'm reading this right it means that Cortex-A7 is dual issue (should mean it decodes two instructions per cycle) and can execute simple ALU/move and branch/call instructions in the dual issue pipeline. However, according to the pipeline description file here:

    https://github.com/m...rm/cortex-a7.md

    It would seem that only ALU instructions with immediate operands can dual issue.

    If you ran a test that showed dual issue didn't work can you show what you did?



    Thanks Exophase,

    I update my code and test again. "It would seem that only ALU instructions with immediate operands can dual issue." you are right.
    cortex-A7 can dual-issue is limited. ARM pipeline can dual issue with the "dual issue pipe"but  ALU instructions with immediate operands  can't dual issue with the neon/floating-pipe.
    The A31 neon ALU performance is the same as the Cortex-a5's,But the Cortex-a7 core really has 64-bit load/store path.
    Cortex-A5 only has 32-bit load/store path.

    Thank you once more!
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