Arm Development Studio forum Cortex-a7 dual-issue ?

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Cortex-a7 dual-issue ?

ray song over 12 years ago

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Gilead Kutnick over 12 years ago

Note: This was originally posted on 20th May 2013 at http://forums.arm.com

Non-symmetric means that the two pipelines support different operations.

I don't have a Cortex-A7 so I can't test it directly, and ARM's TRM documents don't give any information on instruction timing anymore.. but GCC source has some information:

https://github.com/mirrors/gcc/blob/master/gcc/config/arm/arm.c

If I'm reading this right it means that Cortex-A7 is dual issue (should mean it decodes two instructions per cycle) and can execute simple ALU/move and branch/call instructions in the dual issue pipeline. However, according to the pipeline description file here:

https://github.com/mirrors/gcc/blob/master/gcc/config/arm/cortex-a7.md

It would seem that only ALU instructions with immediate operands can dual issue.

If you ran a test that showed dual issue didn't work can you show what you did?
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Gilead Kutnick over 12 years ago

Note: This was originally posted on 20th May 2013 at http://forums.arm.com

Non-symmetric means that the two pipelines support different operations.

I don't have a Cortex-A7 so I can't test it directly, and ARM's TRM documents don't give any information on instruction timing anymore.. but GCC source has some information:

https://github.com/mirrors/gcc/blob/master/gcc/config/arm/arm.c

If I'm reading this right it means that Cortex-A7 is dual issue (should mean it decodes two instructions per cycle) and can execute simple ALU/move and branch/call instructions in the dual issue pipeline. However, according to the pipeline description file here:

https://github.com/mirrors/gcc/blob/master/gcc/config/arm/cortex-a7.md

It would seem that only ALU instructions with immediate operands can dual issue.

If you ran a test that showed dual issue didn't work can you show what you did?
Cancel
Vote up 0 Vote down

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