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Cortex M4 fetch Execute program counter functionning

Gaetan Clavel
Note: This was originally posted on 13th May 2013 at http://forums.arm.com

Hello,

I'm new on this forum and I would like to know some details about the execution of a program on a Cortex M4 ( in a STM32F407 microcontroller). I'm looking for this information because of my studies.

These are my questions :

First I would like to know if there is some kind of predictable execution of the code during the fetch & execute step? It 's quickly mentionned in the user manual and I also read some lines about this in the Cortex A documents but I would like to have some explainations.

I would also like to know how is the program counter (R15 register) functionning? There is a real physical counter which count from 0 to -- when a page is loaded from the flash memory (before to add the value with something else and to store that in R15)?  I mean: when I'm reading a page from the flash memory there is a counter which counts 2 by 2 (because of the lengh of the Thumb mnemonics)? If I'm branching far enough to go on another page the counter would return to 0 ? How does it work?

In addition, from a programming point of view, can I choose to write a part of my code at a precise address of the flash memory, and so creating empty areas between 2 parts of code in the flash? Until know I'm writing a lot of "NOP" before to branch....

Finally, all the registers of the Cortex M4 ( R0 to R15 but also the peripheral registers ...) are physicaly situated at the same place? Or the peripheral register are physicaly situated near from the the corresponding peripheral on the chip?

Thank you very much for yours answers and your help!!!!
Parents
  • Note: This was originally posted on 20th May 2013 at http://forums.arm.com

    the pc and prefetch are all decided by hardware architecture designed by ARM  and have no relationship with software . So prefetch  has some differences between cortex m4 and A series ,they are designed for different use. 

    the buffer is the D/I cache ,all right ? also it is decided by hardware disign , the frequently used data/instruction will be hold in the cache if the cache is full ,then the less used data will be wiped out. the flash is nor/nand flash ? it will be copied into the SRAM ,all the datas processing are in the SRAM ,the buffer is just for high speed data fetch ,just like the prefetch but has different startegy.
Reply
  • Note: This was originally posted on 20th May 2013 at http://forums.arm.com

    the pc and prefetch are all decided by hardware architecture designed by ARM  and have no relationship with software . So prefetch  has some differences between cortex m4 and A series ,they are designed for different use. 

    the buffer is the D/I cache ,all right ? also it is decided by hardware disign , the frequently used data/instruction will be hold in the cache if the cache is full ,then the less used data will be wiped out. the flash is nor/nand flash ? it will be copied into the SRAM ,all the datas processing are in the SRAM ,the buffer is just for high speed data fetch ,just like the prefetch but has different startegy.
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