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ARMv7 vs. Cortex-A9 TRM MPIDR register

Sebastian Huber
Note: This was originally posted on 8th May 2013 at http://forums.arm.com

Hello,

why do the Multiprocessor Affinity Register (MPIDR) definitions in the ARMv7 Architecture Reference (e.g. ARM DDI 0406C.B) and the Cortex-A9 TRM (e.g. ARM DDI 0388E) differ?
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  • Arm Employee Badge
    Note: This was originally posted on 8th May 2013 at http://forums.arm.com

    The ARM ARM gives a generic description of the register, while the TRM gives the processor specific description.  Take one example....

    The ARM ARM describes bits 7:0 as Aff0 - the most significant level of affinity.  It also says that this would typically be used to tell which core you were in within a cluster - in theory allowing up to 256 cores.

    The TRM defines that it only actually uses bit 1:0 - because the A9 only supports up to four cores.  With bits 7:2 (the rest of Aff0)  being 0s.

    The two descriptions aren't contradictory.
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  • Arm Employee Badge
    Note: This was originally posted on 8th May 2013 at http://forums.arm.com

    The ARM ARM gives a generic description of the register, while the TRM gives the processor specific description.  Take one example....

    The ARM ARM describes bits 7:0 as Aff0 - the most significant level of affinity.  It also says that this would typically be used to tell which core you were in within a cluster - in theory allowing up to 256 cores.

    The TRM defines that it only actually uses bit 1:0 - because the A9 only supports up to four cores.  With bits 7:2 (the rest of Aff0)  being 0s.

    The two descriptions aren't contradictory.
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