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How does Cortex-M3 core capture the interrupt signal

Jade Tsien
Note: This was originally posted on 31st March 2013 at http://forums.arm.com

Hi,
I'm using the Cortex-M3 and handling the interrupts of it. It seems that if I set ISR entry to the right interrupt vector number, the core shall do the right ISR  when there is an interrupt signal occure.
But how can the core recogize that which of the interrupt vector number shall the interrupt signal be corresponded to?
For example, if I design a uart for the cortex-m3 to I/O, there occures a uart interrupt, then how does the core distinguish that the interrupt signal is from uart not spi or other peripheral?
NVIC just set the interrupt priority and enable/disable some interrupts, or can NVIC relate the uart interrupt signal to  
[size=2]IRQ#16, if IRQ#16 is the entry of uart ISR?[/size]
[size=2]Well, another question is that I'v set the interrupt vector table in file 'exceptions.c', but when I read the content in [/size]
[size=2]mem 0x00000008, I get 0 not the function address of NMI_Handler. How can I write the ISR entry to the right interrupt vector?[/size]
[size=2]
[/size]
[size=2]Hoping for your answers sincerely![/size]
Parents
  • Note: This was originally posted on 16th April 2013 at http://forums.arm.com


    Each interrupt is assigned a place in the vector table whose base address is configurable, but let's say its 0x1000. So now vector entry for interrupt #16 would be at (0x1000+16*4). There is no magic, so when interrupt 16 happens the CPU automatically fetches the instruction for that interrupt handler by looking up the address from the vector table for that particular interrupt number. That means when you say Uart is interrupt #16 you are deciding that that is the location offset in the vector table which will handle Uart interrupts.



    Thank you for your reply !
    But what concerns me most is how Cortex-M3 core distinguish which outer device has requested for an interrupt? Does NVIC have the function to relate an interrupt signal (in hardware layer) to its IRQ number (in software layer)?
    Thanks again! 

Reply
  • Note: This was originally posted on 16th April 2013 at http://forums.arm.com


    Each interrupt is assigned a place in the vector table whose base address is configurable, but let's say its 0x1000. So now vector entry for interrupt #16 would be at (0x1000+16*4). There is no magic, so when interrupt 16 happens the CPU automatically fetches the instruction for that interrupt handler by looking up the address from the vector table for that particular interrupt number. That means when you say Uart is interrupt #16 you are deciding that that is the location offset in the vector table which will handle Uart interrupts.



    Thank you for your reply !
    But what concerns me most is how Cortex-M3 core distinguish which outer device has requested for an interrupt? Does NVIC have the function to relate an interrupt signal (in hardware layer) to its IRQ number (in software layer)?
    Thanks again! 

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