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IP for access to SODIMM module from Versatile Express LogicTile 13 MG

Svetlana Frolova
Note: This was originally posted on 22nd March 2013 at http://forums.arm.com

Hello! We have a problem with access to SODIMM module from Versatile Express V2f-2xv6 (LogicTile 13) board. Included in DVD v.3 and v.5 file of ARM pl341 DDr2 controller is corrupted (?) and can not be connected to our custom project due to XIlinx ISE "internal error", which occured when I try to connect it. When I try to generate Xilinx IP core by Xilinx Core generator, the problem with pin connectivity in existing .ucf file is occured: existing pin connection on board is not compatible with Xilinx DDR2 PHY.
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  • Note: This was originally posted on 22nd March 2013 at http://forums.arm.com


    Have you tried using the same ISE version the application note was built with, sometimes I have seen issues between different version of tools. The Xilinx controller should work, make sure you are using the same pin contraints as PL341, Xilinx controller might try to pick different ones. If this doesn't work for you I would email support-cards@arm.com
    Liam


    All of other IPs works on my Xilinx ISE v14.4. The problem is that pins ## from VE board are not compartible with Xilinx IP core bank restrictions.
Reply
  • Note: This was originally posted on 22nd March 2013 at http://forums.arm.com


    Have you tried using the same ISE version the application note was built with, sometimes I have seen issues between different version of tools. The Xilinx controller should work, make sure you are using the same pin contraints as PL341, Xilinx controller might try to pick different ones. If this doesn't work for you I would email support-cards@arm.com
    Liam


    All of other IPs works on my Xilinx ISE v14.4. The problem is that pins ## from VE board are not compartible with Xilinx IP core bank restrictions.
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