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ARM cortex a7 cache maintenance operation

Note: This was originally posted on 11th March 2013 at http://forums.arm.com

Hi all:

I move on my last project of ARM cortex-a9 to now cortex-a7, here is a small questions. In A9, seems the pl310 have the ability to invalidate the entire L2 cache by way. But in the A7, seems the maintenance operation are moved to cp15, and I need to invalidate it by set/way?(This significantly increase my simulation time, later i will use the A15, these boot time will be unbearable).

So, do I invalidate l2 cache in a incorrect way? I can not find a good way to invalidate the whole L2 cache in a quick way, please someone help

Best regards

Martin Weidmann over 12 years ago

Note: This was originally posted on 11th March 2013 at http://forums.arm.com

AFAIK there is no alternative. If you want to invalidate the entire L2 on an A7/A15 you have to use set/way operations.

That said, unless you L2RSTDISABLE high the L2 will be automatically invalidated at reset. So there is no need for standard/basic init code to invalidate the L2,
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Peter Harris over 12 years ago

Note: This was originally posted on 11th March 2013 at http://forums.arm.com

Also worth noting that once the CPU is running in multi-core SMP mode you cannot use set-way operations for D-side cache maintenance. You must use clean by MVA to ensure that all of the cache coherency snoops get picked up correctly.
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