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ARM11 MPcore and stale chacheline

Michal Meloun
Note: This was originally posted on 18th February 2013 at http://forums.arm.com

Hello all,

we are in middle of porting FreeBSD to ARM11 MPcore CPU.

Unfortunately, we stuck on strange stale cacheline (probably) issue.

In short, after specific write pattern performed on first core and single write on second, we got stale cacheline on first one.  The write (and yes, it's followed by DSB) from second core is not visible on first CPU.  But after executing s DMB on first core, we got actual data. 

We have verified that both cores are in SMP mode, accessed memory is mapped using 1MB section with shared bit set, without any aliasing.  The hardware is Cavium Networks CNS3420 dual core ARM11 MPcore CPU, revision r2p0.

Unfortunately, we don't have access to any ARM11 MPcore errata. It's here any errata that can cause this problem? It's possible to get errata sheet even we are not ARM customer?

We can post pseudocode that's trigger the issue here, if it's necessary/required.

Many thanks

Michal Meloun
Parents
  • Arm Employee Badge
    Note: This was originally posted on 21st February 2013 at http://forums.arm.com

    One thing I'd like to check.

    I'm not 100% sure it applies to ARM11 MPCore, but on ARMv7A it is not architecturally valid to use clean and invalidate of the whole cache once the CPU is running; you have to do it by set-way or the SCU doesn't necessarily pick up the snoop correctly.

    Additionally why do you have the clean and invalidates everywhere? They shouldn't be needed. The SCU hardware should ensure everything syncs.

    ... and to check the obvious - you have marked these pages as shared in the MMU, and enabled the SCU?
Reply
  • Arm Employee Badge
    Note: This was originally posted on 21st February 2013 at http://forums.arm.com

    One thing I'd like to check.

    I'm not 100% sure it applies to ARM11 MPCore, but on ARMv7A it is not architecturally valid to use clean and invalidate of the whole cache once the CPU is running; you have to do it by set-way or the SCU doesn't necessarily pick up the snoop correctly.

    Additionally why do you have the clean and invalidates everywhere? They shouldn't be needed. The SCU hardware should ensure everything syncs.

    ... and to check the obvious - you have marked these pages as shared in the MMU, and enabled the SCU?
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