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ARM11 MPcore and stale chacheline

Note: This was originally posted on 18th February 2013 at http://forums.arm.com

Hello all,

we are in middle of porting FreeBSD to ARM11 MPcore CPU.

Unfortunately, we stuck on strange stale cacheline (probably) issue.

In short, after specific write pattern performed on first core and single write on second, we got stale cacheline on first one. The write (and yes, it's followed by DSB) from second core is not visible on first CPU. But after executing s DMB on first core, we got actual data.

We have verified that both cores are in SMP mode, accessed memory is mapped using 1MB section with shared bit set, without any aliasing. The hardware is Cavium Networks CNS3420 dual core ARM11 MPcore CPU, revision r2p0.

Unfortunately, we don't have access to any ARM11 MPcore errata. It's here any errata that can cause this problem? It's possible to get errata sheet even we are not ARM customer?

We can post pseudocode that's trigger the issue here, if it's necessary/required.

Many thanks

Michal Meloun

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Martin Weidmann over 12 years ago

Note: This was originally posted on 18th February 2013 at http://forums.arm.com

How do you know that is is a stale line and not a synchronisation problem?
The DMB may just preventing some form of re-ordering changing the timing, thus you get the new(er) data.
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Martin Weidmann over 12 years ago

Note: This was originally posted on 18th February 2013 at http://forums.arm.com

How do you know that is is a stale line and not a synchronisation problem?
The DMB may just preventing some form of re-ordering changing the timing, thus you get the new(er) data.
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