Arm Community
Site
Search
User
Site
Search
User
Groups
Research Collaboration and Enablement
DesignStart
Education Hub
Innovation
Open Source Software and Platforms
Forums
AI and ML forum
Architectures and Processors forum
Arm Development Platforms forum
Arm Development Studio forum
Arm Virtual Hardware forum
Automotive forum
Compilers and Libraries forum
Graphics, Gaming, and VR forum
High Performance Computing (HPC) forum
Infrastructure Solutions forum
Internet of Things (IoT) forum
Keil forum
Morello Forum
Operating Systems forum
SoC Design and Simulation forum
中文社区论区
Blogs
AI and ML blog
Announcements
Architectures and Processors blog
Automotive blog
Graphics, Gaming, and VR blog
High Performance Computing (HPC) blog
Infrastructure Solutions blog
Innovation blog
Internet of Things (IoT) blog
Operating Systems blog
Research Articles
SoC Design and Simulation blog
Tools, Software and IDEs blog
中文社区博客
Support
Arm Support Services
Documentation
Downloads
Training
Arm Approved program
Arm Design Reviews
Community Help
More
Cancel
Support forums
Arm Development Studio forum
wrong cycle timing of instructions on ARM11
Jump...
Cancel
Locked
Locked
Replies
6 replies
Subscribers
121 subscribers
Views
3224 views
Users
0 members are here
Options
Share
More actions
Cancel
Related
How was your experience today?
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion
wrong cycle timing of instructions on ARM11
Offline
chandrakala reddy
over 9 years ago
Note: This was originally posted on 4th February 2013 at
http://forums.arm.com
Hi,
Iam using RVDS3.0 for ARM11. some of the instructions are not executing in the time specified by the ARM documentation. for example, according to ARM documents, SMLAD instruction has to take 1 cycle for execution and 2 stalls if the result is immediatly used. but in real time, it is taking 2 cycles for execution. is it a bug on RVDS3.0 or am i missing any thing here. can any one please help me out.
Regards,
Chandrakala
Parents
Offline
chandrakala reddy
over 9 years ago
Note: This was originally posted on 4th February 2013 at
http://forums.arm.com
Hi,
Thanks for the reply. there is no register dependency in the code.
Following is my code
SMLAD r0, r1, r2, r3
SMLAD r4, r5, r6, r7
SMLAD r8, r9, r10, r11
SMLAD r12, lr, r1, r6
Is there any issue with the code?
Regards,
Chandrakala
Cancel
Up
0
Down
Cancel
Reply
Offline
chandrakala reddy
over 9 years ago
Note: This was originally posted on 4th February 2013 at
http://forums.arm.com
Hi,
Thanks for the reply. there is no register dependency in the code.
Following is my code
SMLAD r0, r1, r2, r3
SMLAD r4, r5, r6, r7
SMLAD r8, r9, r10, r11
SMLAD r12, lr, r1, r6
Is there any issue with the code?
Regards,
Chandrakala
Cancel
Up
0
Down
Cancel
Children
No data