• Locked Locked
  • Replies 2 replies
  • Subscribers 119 subscribers
  • Views 2737 views
  • Users 0 members are here
Options
Related
How was your experience today?
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

difference between saved copy and banked copy

Rui Ma
Note: This was originally posted on 15th January 2013 at http://forums.arm.com

Hi there,

I am reading ARM architecture manual v7, part B.
In the discretion of system register banks on page 1144, it refers SPs with a term as "banked copy"; while for the SPSRs, it uses "saved copy".
Is there a difference? I mean on the implementation of the micro-architecture.
Thanks in advance!
Parents
  • Arm Employee Badge
    Note: This was originally posted on 16th January 2013 at http://forums.arm.com

    In this case you confusing the name and the description...

    ARMv7-A/R processors have several "modes", these include User mode, IRQ mode, Abort mode, etc...

    Some processors registers are common.  This means that whichever processor mode you are in, you will see the same copy of that register.  Examples of common registers are r0 and r1.

    Other register are "banked" this means that are multiple physical copies of that register, and which copy you see depends on the mode you're currently in.  So when in Abort mode, you see the Abort mode copy of r13.  Typically banked registers are sp (r13), lr (r14) and spsr.

    Now SPSR stands for Save Program Status Register.  As it happens, the SPSR is a banked register.

    For completeness, the SPSR is used in exception handling.  When you take an exception you change from your current mode to the mode associated with that exception.  For example, an interrupt could take you from User mode into IRQ mode.  There is a register called the CPSR (current program status register) which stores various bits of configuration, such as what mode you are in.  When you taken an exception, the CPSR is automatically copied into the SPSR.   Hence "saved".
Reply
  • Arm Employee Badge
    Note: This was originally posted on 16th January 2013 at http://forums.arm.com

    In this case you confusing the name and the description...

    ARMv7-A/R processors have several "modes", these include User mode, IRQ mode, Abort mode, etc...

    Some processors registers are common.  This means that whichever processor mode you are in, you will see the same copy of that register.  Examples of common registers are r0 and r1.

    Other register are "banked" this means that are multiple physical copies of that register, and which copy you see depends on the mode you're currently in.  So when in Abort mode, you see the Abort mode copy of r13.  Typically banked registers are sp (r13), lr (r14) and spsr.

    Now SPSR stands for Save Program Status Register.  As it happens, the SPSR is a banked register.

    For completeness, the SPSR is used in exception handling.  When you take an exception you change from your current mode to the mode associated with that exception.  For example, an interrupt could take you from User mode into IRQ mode.  There is a register called the CPSR (current program status register) which stores various bits of configuration, such as what mode you are in.  When you taken an exception, the CPSR is automatically copied into the SPSR.   Hence "saved".
Children
No data