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load image into cache and execute it in cache

yitian bu
Note: This was originally posted on 31st January 2013 at http://forums.arm.com

Hi Experts:

    i have heard that some ARM platform providers load their bootloader into L2 cache, and execute the bootloader in L2 cache directly.

    how can this work? do they add some logic inside silicon to make this work?

    as my understanding, cache has differnt architecture from normal sram, how can CPU recognize the L2 cache as a normal sram and execute image in it directly?



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  • Arm Employee Badge
    Note: This was originally posted on 1st February 2013 at http://forums.arm.com

    I cannot understand why the newer Cortex-A cores cannot support this trick?
    Their cache implementations don't implement cache lockdown, so you can't keep the data in the cache, and all cache therefore needs to be backed by real memory.
    and for TCM, i remembered that ARM9 can also support this, why doesn't Cortex-A support this?
    TCM is really only needed for real-time environments, so the Cortex-R cores still implement it. Cortex-A is targeting "Big OS" - Linux, Symbian, Android, Windows RT, etc. In these environments it is very hard to make use of dedicated memories, and they complicate / slow down the L1 memory hierarchy, so it is not supported.
    i suppose the TCM is similar to cache and can be integrated to all ARM core, is it correct?
    See above.HTH, Iso
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  • Arm Employee Badge
    Note: This was originally posted on 1st February 2013 at http://forums.arm.com

    I cannot understand why the newer Cortex-A cores cannot support this trick?
    Their cache implementations don't implement cache lockdown, so you can't keep the data in the cache, and all cache therefore needs to be backed by real memory.
    and for TCM, i remembered that ARM9 can also support this, why doesn't Cortex-A support this?
    TCM is really only needed for real-time environments, so the Cortex-R cores still implement it. Cortex-A is targeting "Big OS" - Linux, Symbian, Android, Windows RT, etc. In these environments it is very hard to make use of dedicated memories, and they complicate / slow down the L1 memory hierarchy, so it is not supported.
    i suppose the TCM is similar to cache and can be integrated to all ARM core, is it correct?
    See above.HTH, Iso
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