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load image into cache and execute it in cache

yitian bu
Note: This was originally posted on 31st January 2013 at http://forums.arm.com

Hi Experts:

    i have heard that some ARM platform providers load their bootloader into L2 cache, and execute the bootloader in L2 cache directly.

    how can this work? do they add some logic inside silicon to make this work?

    as my understanding, cache has differnt architecture from normal sram, how can CPU recognize the L2 cache as a normal sram and execute image in it directly?



Best Regards
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  • Note: This was originally posted on 2nd February 2013 at http://forums.arm.com


    Their cache implementations don't implement cache lockdown, so you can't keep the data in the cache, and all cache therefore needs to be backed by real memory.TCM is really only needed for real-time environments, so the Cortex-R cores still implement it. Cortex-A is targeting "Big OS" - Linux, Symbian, Android, Windows RT, etc. In these environments it is very hard to make use of dedicated memories, and they complicate / slow down the L1 memory hierarchy, so it is not supported.See above.HTH, Iso


    thank you for your reply.

    i want to give a rough imagination about the trick, please correct me, thanks:

    0. suppose L2 cache size is 1MB, 8-Way, 32Bytes cache line. the index number is 1MB/8/32=4096.

    1. suppose address region 0xf0000000~0xf0001000 of CPU is dedicated for this trick, and read/write to this area will not give any bus error. reading returns 0, writing does not update data.

    2. in rom code, use a loop to read region 0xf0000000~0xf0001000, which can let whole of this region are cached in Way-0.

    3. lock down Way-0

    4. read second boot loader from falsh to region 0xf0000000~0xf0001000, jump to second bootloader.
Reply
  • Note: This was originally posted on 2nd February 2013 at http://forums.arm.com


    Their cache implementations don't implement cache lockdown, so you can't keep the data in the cache, and all cache therefore needs to be backed by real memory.TCM is really only needed for real-time environments, so the Cortex-R cores still implement it. Cortex-A is targeting "Big OS" - Linux, Symbian, Android, Windows RT, etc. In these environments it is very hard to make use of dedicated memories, and they complicate / slow down the L1 memory hierarchy, so it is not supported.See above.HTH, Iso


    thank you for your reply.

    i want to give a rough imagination about the trick, please correct me, thanks:

    0. suppose L2 cache size is 1MB, 8-Way, 32Bytes cache line. the index number is 1MB/8/32=4096.

    1. suppose address region 0xf0000000~0xf0001000 of CPU is dedicated for this trick, and read/write to this area will not give any bus error. reading returns 0, writing does not update data.

    2. in rom code, use a loop to read region 0xf0000000~0xf0001000, which can let whole of this region are cached in Way-0.

    3. lock down Way-0

    4. read second boot loader from falsh to region 0xf0000000~0xf0001000, jump to second bootloader.
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