• Locked Locked
  • Replies 6 replies
  • Subscribers 119 subscribers
  • Views 4483 views
  • Users 0 members are here
Options
Related
How was your experience today?
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

load image into cache and execute it in cache

yitian bu
Note: This was originally posted on 31st January 2013 at http://forums.arm.com

Hi Experts:

    i have heard that some ARM platform providers load their bootloader into L2 cache, and execute the bootloader in L2 cache directly.

    how can this work? do they add some logic inside silicon to make this work?

    as my understanding, cache has differnt architecture from normal sram, how can CPU recognize the L2 cache as a normal sram and execute image in it directly?



Best Regards
Parents
  • Note: This was originally posted on 1st February 2013 at http://forums.arm.com


    You can play some tricks using cache lockdown of some ways in the L2 cache, but it is increasingly an option not implemented in newer Cortex-A profile cores so not always available.

    Cortex-R profile cores tend to have better alternatives available - such as TCM.


    thank you isogen74, could you please provide some documents about the implementation details of this trick?

    i cannot understand why the newer Cortex-A cores cannot support this trick?

    and for TCM, i remembered that ARM9 can also support this, why doesn't Cortex-A support this?

    i suppose the TCM is similar to cache and can be integrated to all ARM core, is it correct?
Reply
  • Note: This was originally posted on 1st February 2013 at http://forums.arm.com


    You can play some tricks using cache lockdown of some ways in the L2 cache, but it is increasingly an option not implemented in newer Cortex-A profile cores so not always available.

    Cortex-R profile cores tend to have better alternatives available - such as TCM.


    thank you isogen74, could you please provide some documents about the implementation details of this trick?

    i cannot understand why the newer Cortex-A cores cannot support this trick?

    and for TCM, i remembered that ARM9 can also support this, why doesn't Cortex-A support this?

    i suppose the TCM is similar to cache and can be integrated to all ARM core, is it correct?
Children
No data