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SMC instruction

Dm Sh
Note: This was originally posted on 22nd January 2013 at http://forums.arm.com

Good day.

I have a question - where I can get the #immediate value (4bit) in Secure Monitor Exception Handler, when called SMC instruction with non zero parametr - #imm-4 ?
Don't found this value in any registers.


From ARM documentation.
-------------------------------------

SMC
Secure Monitor Call.


Syntax
SMC{cond} #imm4 where:

[i]imm4[/i]is a 4-bit immediate value. This is ignored by the ARM processor, but can be used by the SMC exception handler to determine what service is being requested.


Thanks.
Parents
  • Note: This was originally posted on 22nd January 2013 at http://forums.arm.com

    The immediate value passed with the SMC instruction can be retrieved by reading back the SMC instruction opcode. The address of SMC instruction can known from the link register of monitor mode. Consider the following code sequence:

    IA        Instructions
    ------------------------------------------
    ...     ...
    0x840    i0
    0x844    i1
    0x848    SMC #10
    0x84C    i3
    ....              ...

    where IA is the instruction address

    When the SMC instruction is executed, a software exception is generated changing the CPU state with LR_mon/R14_mon getting updated with 0x84C (basically address of SMC instruction+4 irrespective of whether the SMC was executed in ARM or Thumb mode). So in the monitor exception handler, we can read back the SMC instruction opcode and extract the immediate value in the following way:
    ... initial code for monitor handler....
    LDR r0, [r14, # - 4]
    AND r0, r0, #0xF   (The immediate value is encoded in bits[3:0] of SMC instruction for both ARM and Thumb encoding)

    Hope this helps.
Reply
  • Note: This was originally posted on 22nd January 2013 at http://forums.arm.com

    The immediate value passed with the SMC instruction can be retrieved by reading back the SMC instruction opcode. The address of SMC instruction can known from the link register of monitor mode. Consider the following code sequence:

    IA        Instructions
    ------------------------------------------
    ...     ...
    0x840    i0
    0x844    i1
    0x848    SMC #10
    0x84C    i3
    ....              ...

    where IA is the instruction address

    When the SMC instruction is executed, a software exception is generated changing the CPU state with LR_mon/R14_mon getting updated with 0x84C (basically address of SMC instruction+4 irrespective of whether the SMC was executed in ARM or Thumb mode). So in the monitor exception handler, we can read back the SMC instruction opcode and extract the immediate value in the following way:
    ... initial code for monitor handler....
    LDR r0, [r14, # - 4]
    AND r0, r0, #0xF   (The immediate value is encoded in bits[3:0] of SMC instruction for both ARM and Thumb encoding)

    Hope this helps.
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