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XN bit support on ARMv7 Cortex A15

taani E
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  • Arm Employee Badge
    Note: This was originally posted on 11th June 2013 at http://forums.arm.com

    Realize this is an old post, but I hit it with a Google search, so I thought worth posting "probable cause".

    I suspect your test case is incorrect. You mention you are pushing executable code onto the stack and sometimes getting a fault, and sometimes not.

    ARMv7 does not include hardware memory coherency between I-cache and D-cache, so you are getting a cache coherency problem where you have written the code to the D cache, but the I cache is probably trying to execute the old data rather than your new code. What you are trying to do is invalid without manual cache operations to ensure I and D sides of the memory system see the same data values.

    HTH,
    Iso
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  • Arm Employee Badge
    Note: This was originally posted on 11th June 2013 at http://forums.arm.com

    Realize this is an old post, but I hit it with a Google search, so I thought worth posting "probable cause".

    I suspect your test case is incorrect. You mention you are pushing executable code onto the stack and sometimes getting a fault, and sometimes not.

    ARMv7 does not include hardware memory coherency between I-cache and D-cache, so you are getting a cache coherency problem where you have written the code to the D cache, but the I cache is probably trying to execute the old data rather than your new code. What you are trying to do is invalid without manual cache operations to ensure I and D sides of the memory system see the same data values.

    HTH,
    Iso
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