Arm Development Studio forum Re-Entrant and nesting of low priority Interrupts on Cortex M4

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Re-Entrant and nesting of low priority Interrupts on Cortex M4

Note: This was originally posted on 4th December 2012 at http://forums.arm.com

Hi All,

I have tried to implement Re-Entrant and nesting of low priority Interrupts on Cortex M4 even if NVIC does not allow this feature.
I am using Freescale's MK60FN1M0VLQ12 processor.
I am trying to implement logic such that NVIC can serve any interrupt irrespective of its priority.

For that i have implemented following logic -----
1 When interrupt occurs , NVIC pushes frame of particular registers to stack ( r0,r1,r2,r3,r12,LR,PC,XPSR - for non floating point execution ). In IRQ Handler, i have
acknowledged the interrupt and then I have pushed dummy frame to stack which contains Reset Value Of XPSR, Address of MY ISR Routine, Original LR, R12 = 0,R3 = 0,
R2 = 0, R1 =0, R0 =0. Then i have used (BX LR) to return from handler.
2. So when core returns from handler it will pop dummy frame and will go to MY ISR routine.
3. In MY ISR routine i have done my stuff and then load the registers r0-r4 ,r12, LR,XPSR and PC with original values from stack frame pushed by NVIC.

Now i am able to return successfully to point from where interrupt occurred. Therefore now I am able to nest low priority interrupts even if NVIC executing higher priority interrupt.But sometimes processor goes to Hard Fault Exception.

After that i have implemented same logic for floating point execution in which I have added floating point registers S0 - S15 and FPSCR. But still processor goes to hard fault exception once in a while.

So can anybody suggest what did i miss?

OR has anybody implemented the nesting of low priority interrupts on CORTEX-M core.

Basically my purpose is to serve any interrupt as soon as it occurs irrespective of its priority which can be done in ARM7.

Thanks !!!