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NIC-400 Interconnect generation issue

narendra kandimalla
Note: This was originally posted on 27th December 2012 at http://forums.arm.com

Hi ,

I am using NIC-400 for AXI 128x64 interconnect. 1-slave X 2-masters.

Read transactions with arsize=4,arlen(burst lenth)=16 and burst size=3 doesn't give any issues.




BUT  below read scenario is giving issue..........


  Scenario:- AXI Read Transaction, Incrementing Burst with Burst Length 1.

Data for "arsize = 3". --Transaction Size = 8Bytes.

That means we are requesting 64-byte data from master side. In the simulation waveforms I can see a valid 64-bit data & 64-bit Zeros as valid next data each time.

In waveforms i can see XBAR selecting both lower 64-bit & higher 64-bit data of each 128-bit data it receives from slave.which its transfers as 2-valid data transactions to master.


During this process its missing to transfer another valid data it requested master(in this place Its transfering Valid ZERO data).

Is it The issue with XBAR generation?





Thanks,

Narendra





Parents
  • Arm Employee Badge
    Note: This was originally posted on 9th January 2013 at http://forums.arm.com

    Narendra,

    For your first question I'd imagine that as NIC-400 is a fairly new product that you would have licensed it directly from ARM, and so you could use the support agreement you have with them to contact their support group directly. They are more likely to understand the issue you are observing, or be able to investigate them.

    For the second question, as you have ARLEN=0 this means only one beat in this burst, so there wouldn't be any "consecutive" transfers. The ARADDR value would dictate which half of the 128 bit data bus should be used for the single transfer from the slave. If you did have a burst longer than one transfer, as it is an incrementing burst you should see data appear on alternating halves of the wider data bus.

    JD
Reply
  • Arm Employee Badge
    Note: This was originally posted on 9th January 2013 at http://forums.arm.com

    Narendra,

    For your first question I'd imagine that as NIC-400 is a fairly new product that you would have licensed it directly from ARM, and so you could use the support agreement you have with them to contact their support group directly. They are more likely to understand the issue you are observing, or be able to investigate them.

    For the second question, as you have ARLEN=0 this means only one beat in this burst, so there wouldn't be any "consecutive" transfers. The ARADDR value would dictate which half of the 128 bit data bus should be used for the single transfer from the slave. If you did have a burst longer than one transfer, as it is an incrementing burst you should see data appear on alternating halves of the wider data bus.

    JD
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