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How to set dram region to cacheable?

china liu
Note: This was originally posted on 31st October 2012 at http://forums.arm.com

hi, experts:
I am a newcomer to ARM world.
I was working x86 platform in these years.

So, i have a question about how to set dram region's cacheable attributes.
Take my ARM development board as an example:
It has 1GByte DRAM, 4MB NOR Flash, 64MB Nand Flash.
So:
1. How to set some parts of 1GByte DRAM to cacheable(write back)?
2. How to set 4MByte NOR Flash region to cacheable , to enhance uboot's execution speed?

With x86 CPU, it had MTRR registers to do these things, so how to do these things on ARM platform?
I have read some arm documents, it seemed doing these things by creating page tables , right?

Any tips will be appreciated!

best wishes,
Parents
  • Note: This was originally posted on 23rd November 2012 at http://forums.arm.com

    The cache mechanism is personal to the processor and memory is shared across masters. It depends how you have managed/partition your memory. Configuring memory attributes from the cache behavior is where you have to work with page tables (in case of processors such as Cortex-A9 with MMU). Again how your system is configured drives the section/page size where you have to program the descriptors. If you have a memory which is divided into 1MB section for an example, then you have to control the cache attributes per 1MB.

    On your other reference to L2 Cache with Cortex-A9, this is an external IP on AXI bus. What exactly is your concern with L2 Cache?

    Hi,
    I have a very similar question !
    i would like to separate my DDR memory into 2 sections :
    one, used by the processor only, this section have to be cacheable
    the other shared with external processes. this section mus be set as a device.
    i'm working on a Cortex A9 inside a Xilinx's Zynq.
    i could find a library with these functions :

    void Xil_DCacheInvalidateLine(unsigned int adr);
    void Xil_DCacheFlushLine(unsigned int adr);
    void Xil_DCacheStoreLine(unsigned int adr);
    void Xil_ICacheInvalidateLine(unsigned int adr);

    void Xil_L1DCacheEnable(void);
    void Xil_L1DCacheDisable(void);
    void Xil_L1DCacheInvalidate(void);
    void Xil_L1DCacheInvalidateLine(unsigned int adr);
    void Xil_L1DCacheInvalidateRange(unsigned int adr, unsigned len);
    void Xil_L1DCacheFlush(void);
    void Xil_L1DCacheFlushLine(unsigned int adr);
    void Xil_L1DCacheFlushRange(unsigned int adr, unsigned len);
    void Xil_L1DCacheStoreLine(unsigned int adr);

    void Xil_L1ICacheEnable(void);
    void Xil_L1ICacheDisable(void);
    void Xil_L1ICacheInvalidate(void);
    void Xil_L1ICacheInvalidateLine(unsigned int adr);
    void Xil_L1ICacheInvalidateRange(unsigned int adr, unsigned len);

    void Xil_L2CacheEnable(void);
    void Xil_L2CacheDisable(void);
    void Xil_L2CacheInvalidate(void);
    void Xil_L2CacheInvalidateLine(unsigned int adr);
    void Xil_L2CacheInvalidateRange(unsigned int adr, unsigned len);
    void Xil_L2CacheFlush(void);
    void Xil_L2CacheFlushLine(unsigned int adr);
    void Xil_L2CacheFlushRange(unsigned int adr, unsigned len);
    void Xil_L2CacheStoreLine(unsigned int adr);

    but it doesn't enable disable cache for only a section of the DDR.

    i saw there is a stuff called PL 310 who looks like the L2 Cache, and also some explanation about MMU and translation table but i could not find
    a simple example that i could modify to make the job. I hope someone could help !!
    regards.
    Thomas.
Reply
  • Note: This was originally posted on 23rd November 2012 at http://forums.arm.com

    The cache mechanism is personal to the processor and memory is shared across masters. It depends how you have managed/partition your memory. Configuring memory attributes from the cache behavior is where you have to work with page tables (in case of processors such as Cortex-A9 with MMU). Again how your system is configured drives the section/page size where you have to program the descriptors. If you have a memory which is divided into 1MB section for an example, then you have to control the cache attributes per 1MB.

    On your other reference to L2 Cache with Cortex-A9, this is an external IP on AXI bus. What exactly is your concern with L2 Cache?

    Hi,
    I have a very similar question !
    i would like to separate my DDR memory into 2 sections :
    one, used by the processor only, this section have to be cacheable
    the other shared with external processes. this section mus be set as a device.
    i'm working on a Cortex A9 inside a Xilinx's Zynq.
    i could find a library with these functions :

    void Xil_DCacheInvalidateLine(unsigned int adr);
    void Xil_DCacheFlushLine(unsigned int adr);
    void Xil_DCacheStoreLine(unsigned int adr);
    void Xil_ICacheInvalidateLine(unsigned int adr);

    void Xil_L1DCacheEnable(void);
    void Xil_L1DCacheDisable(void);
    void Xil_L1DCacheInvalidate(void);
    void Xil_L1DCacheInvalidateLine(unsigned int adr);
    void Xil_L1DCacheInvalidateRange(unsigned int adr, unsigned len);
    void Xil_L1DCacheFlush(void);
    void Xil_L1DCacheFlushLine(unsigned int adr);
    void Xil_L1DCacheFlushRange(unsigned int adr, unsigned len);
    void Xil_L1DCacheStoreLine(unsigned int adr);

    void Xil_L1ICacheEnable(void);
    void Xil_L1ICacheDisable(void);
    void Xil_L1ICacheInvalidate(void);
    void Xil_L1ICacheInvalidateLine(unsigned int adr);
    void Xil_L1ICacheInvalidateRange(unsigned int adr, unsigned len);

    void Xil_L2CacheEnable(void);
    void Xil_L2CacheDisable(void);
    void Xil_L2CacheInvalidate(void);
    void Xil_L2CacheInvalidateLine(unsigned int adr);
    void Xil_L2CacheInvalidateRange(unsigned int adr, unsigned len);
    void Xil_L2CacheFlush(void);
    void Xil_L2CacheFlushLine(unsigned int adr);
    void Xil_L2CacheFlushRange(unsigned int adr, unsigned len);
    void Xil_L2CacheStoreLine(unsigned int adr);

    but it doesn't enable disable cache for only a section of the DDR.

    i saw there is a stuff called PL 310 who looks like the L2 Cache, and also some explanation about MMU and translation table but i could not find
    a simple example that i could modify to make the job. I hope someone could help !!
    regards.
    Thomas.
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