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How to set dram region to cacheable?

china liu
Note: This was originally posted on 31st October 2012 at http://forums.arm.com

hi, experts:
I am a newcomer to ARM world.
I was working x86 platform in these years.

So, i have a question about how to set dram region's cacheable attributes.
Take my ARM development board as an example:
It has 1GByte DRAM, 4MB NOR Flash, 64MB Nand Flash.
So:
1. How to set some parts of 1GByte DRAM to cacheable(write back)?
2. How to set 4MByte NOR Flash region to cacheable , to enhance uboot's execution speed?

With x86 CPU, it had MTRR registers to do these things, so how to do these things on ARM platform?
I have read some arm documents, it seemed doing these things by creating page tables , right?

Any tips will be appreciated!

best wishes,
Parents
  • Arm Employee Badge
    Note: This was originally posted on 1st November 2012 at http://forums.arm.com

    The answer partly depends on which processor you are using.

    Assuming that you are using a Cortex-A processor, then it's in the translation tables.  On reset, the Memory Management Unit (MMU) is disabled.  It is the MMU which is used to define which addresses are cacheable, readable, etc....  To turn on the MMU you must first set up the translation tables.  These are the tables which tell the MMU what the attributes are.
Reply
  • Arm Employee Badge
    Note: This was originally posted on 1st November 2012 at http://forums.arm.com

    The answer partly depends on which processor you are using.

    Assuming that you are using a Cortex-A processor, then it's in the translation tables.  On reset, the Memory Management Unit (MMU) is disabled.  It is the MMU which is used to define which addresses are cacheable, readable, etc....  To turn on the MMU you must first set up the translation tables.  These are the tables which tell the MMU what the attributes are.
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