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Cortex A9 WFE instruction not working as expected

Rich Podraza
Note: This was originally posted on 10th October 2012 at http://forums.arm.com

I'm trying to do a simple test with WFE instruction and EVENTI/O signals. I'm trying to have one A9 enter a wait state with WFE, and have another A9 do some dummy operations while the first is waiting, then do SEV instruction to signal from its SIGNALO to the other A9's SIGNALI. I can verify with my simulation envronment that this signal fires. However, the first A9 is not waiting, it breezes right by the WFE instruction. No assembler warning indicating these instructions aren't supported.

My best clue is in the assembler guide there is the line "If the Event Register is set, WFE clears it and returns immediately," it sounds like this might be happening, but I can't find any reference to "Event Register" in the Cortex A9 TRM, so I'm not sure if this is active by default in my system or what.

Any ideas? Thanks!
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  • Note: This was originally posted on 16th October 2012 at http://forums.arm.com


    Just wanted to bump my last question...I have been continuing to look into it and can't make sense of it. Very strange that STREX returns 1 yet the store occurs in memory. Does anyone have an idea?


    Nevermind guys, I figured this out. It was a problem with my simulation environment, the memory model did not have an exclusive monitor enabled. Still seems like wrong behavior to me, I feel like the memory write shouldn't have occurred but maybe this is a problem with the RAM model implementation.
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  • Note: This was originally posted on 16th October 2012 at http://forums.arm.com


    Just wanted to bump my last question...I have been continuing to look into it and can't make sense of it. Very strange that STREX returns 1 yet the store occurs in memory. Does anyone have an idea?


    Nevermind guys, I figured this out. It was a problem with my simulation environment, the memory model did not have an exclusive monitor enabled. Still seems like wrong behavior to me, I feel like the memory write shouldn't have occurred but maybe this is a problem with the RAM model implementation.
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