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Assertion of IRQS is not causing calling of ISR

Lokesh Kumar
Note: This was originally posted on 4th September 2012 at http://forums.arm.com

Hi,

With my current flow, when I am asserting legacy nIRQ I am able to jump to ISR, but not when asserting IRQS[0].
I have enabled interrupts as below
[size=2]CPSIE   ifa, #18

and configured [size=2]Interrupt Security ([/size][/size][size=2][size=2]ICDISR), [size=2][/size][/size][/size][size=2][size=2][size=2][size=2]Interrupt Edge Trigger Config ([/size]ICDIF),[size=2]Interrupt Priority (ICDIPR)[/size][/size][/size][/size],[size=2]Interrupt Target Processor (ICDIPTR),[size=2]Interrupt Enable (ICDISER),[size=2]Interrupt Priority Mask (ICCPMR),[size=2]Interrupt Binary Point (ICCBPR),[size=2]Interface Control Register (ICCICR),[size=2]Distributor Control Register (ICDDCR)

Am I missing something?
Is something separate need to be done, when using IRQS interrupts?

Thanks
Lokesh
[/size][/size][/size][/size][/size][/size]
Parents
  • Arm Employee Badge
    Note: This was originally posted on 6th September 2012 at http://forums.arm.com

    I've only skimmed through the code, but I spotted one thing you might want to look into.

    You are writing 0x1F into the CPU Interface Control Register (ICCICR), looking at the GIC spec...

      [3] = FIQEn

    Setting this bit means that "secure" interrupts are delivered as FIQ exceptions - not IRQs.  Earlier in the code you zeroed the Interrupt Security (ICDISR), making all your interrupts secure.  So they're all going to be delivered as FIQs.

    Have you cleared the CPSR.F bit?
Reply
  • Arm Employee Badge
    Note: This was originally posted on 6th September 2012 at http://forums.arm.com

    I've only skimmed through the code, but I spotted one thing you might want to look into.

    You are writing 0x1F into the CPU Interface Control Register (ICCICR), looking at the GIC spec...

      [3] = FIQEn

    Setting this bit means that "secure" interrupts are delivered as FIQ exceptions - not IRQs.  Earlier in the code you zeroed the Interrupt Security (ICDISR), making all your interrupts secure.  So they're all going to be delivered as FIQs.

    Have you cleared the CPSR.F bit?
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