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Assertion of IRQS is not causing calling of ISR

Lokesh Kumar
Note: This was originally posted on 4th September 2012 at http://forums.arm.com

Hi,

With my current flow, when I am asserting legacy nIRQ I am able to jump to ISR, but not when asserting IRQS[0].
I have enabled interrupts as below
[size=2]CPSIE   ifa, #18

and configured [size=2]Interrupt Security ([/size][/size][size=2][size=2]ICDISR), [size=2][/size][/size][/size][size=2][size=2][size=2][size=2]Interrupt Edge Trigger Config ([/size]ICDIF),[size=2]Interrupt Priority (ICDIPR)[/size][/size][/size][/size],[size=2]Interrupt Target Processor (ICDIPTR),[size=2]Interrupt Enable (ICDISER),[size=2]Interrupt Priority Mask (ICCPMR),[size=2]Interrupt Binary Point (ICCBPR),[size=2]Interface Control Register (ICCICR),[size=2]Distributor Control Register (ICDDCR)

Am I missing something?
Is something separate need to be done, when using IRQS interrupts?

Thanks
Lokesh
[/size][/size][/size][/size][/size][/size]
Parents
  • Note: This was originally posted on 5th September 2012 at http://forums.arm.com

    Hi ttfn,

    Yes you are right I am using cortex A9 MP core
    Here is what I am configuring
      ;;; --------------------------------
    ;;; -Interrupt Security (ICDISR) (ICDISR0 is banked per processor)
    ;;; --------------------------------
        ; Define the security for this SPI interrupt
    [ :DEF:VERBOSE
        MESSAGE "Setting Interrupt Security\n"
    ]
        LDR  r2, =0x00000000 ; 1 = non-secure, 0 = secure
        ADD  r3, r11, #0x80
        MOV  r0, #0
    int_secure_loop
        STR  r2, [r3]
        ADD  r0, r0, #0x1
        ADD  r3, r3, #0x4
    ;    CMP  r0, #0x08 ;#NUM_INT_LOOPS  ;only need 8 times
        CMP  r0, #NUM_INT_LOOPS 
        BNE   int_secure_loop
    ;;; --------------------------------
    ;;; -Interrupt Edge Trigger Config (ICDIFR)
    ;;; --------------------------------
    [ :DEF:VERBOSE
        MESSAGE "Setting Interrupt Trigger Cfg\n"
    ]
        LDR  r2, =0xffffffff ; 1 = edge, 0 = level
        ADD  r3, r11, #0xc00
        MOV  r0, #0
    int_edge_cfg_loop
        STR  r2, [r3]
        ADD  r0, r0, #0x1
        ADD  r3, r3, #0x4
    ;    CMP  r0, #0x10 ;#NUM_INT_LOOPS
        CMP  r0, #NUM_INT_LOOPS
        BNE   int_edge_cfg_loop

    ;;; --------------------------------
    ;;; -Interrupt Priority (ICDIPR)
    ;;; --------------------------------
    [ :DEF:VERBOSE
        MESSAGE "Set Priority (greater than 0 to avoid masking)\n"
    ]
        ADD  r3, r11, #0x400
        LDR  r1, =0x08080808 ;; just make all priorities the same for this test
        MOV  r0, #0
    set_pri_loop   
    ;    STR  r1, [r3, #0x4]
        STR  r1, [r3]
        ADD  r0, r0, #0x1
        ADD  r3, r3, #0x4
        CMP  r0, #NUM_INT_LOOPS
        BNE   set_pri_loop
       
    ;;; --------------------------------
    ;;; -Interrupt Target Processor (ICDIPTR)
    ;;; --------------------------------
        ; Define the target for this SPI interrupt
    [ :DEF:VERBOSE
        MESSAGE "Setting Interrupt Targets\n"
    ]
    ; --- For example purposes, we'll have one processor as an individual target per interrupt
        LDR  r2, =0x01010101 ; See GIC Arch spec : one byte per interrupt : 1 = CPU0, 2 = CPU1, 4=CPU2, 8=CPU3
        ADD  r3, r11, #0x800
        MOV  r0, #0
    int_target_loop
        STR  r2, [r3, #32] ;; Int ID's 0-31 are banked per CPU and not programmed for target processors
        ADD  r0, r0, #0x1
        ADD  r3, r3, #0x4
        CMP  r0, #NUM_INT_LOOPS
        BNE   int_target_loop

    ;;; --------------i------------------
    ;;; -Interrupt Enable (ICDISER)
    ;;; --------------------------------
        ; Now we need to enable the intterupts
    [ :DEF:VERBOSE
        MESSAGE "Enable Interrupts\n"
    ]
        LDR  r2, =0xffffffff
        ADD  r3, r11, #0x100
        MOV  r0, #0
    set_enable_loop
    ;    STR  r2, [r3, #0x4]
        STR  r2, [r3]
        ADD  r0, r0, #0x1
        ADD  r3, r3, #0x4
    ;    CMP  r0, #0x4 ;#NUM_INT_LOOPS
        CMP  r0, #NUM_INT_LOOPS
        BNE   set_enable_loop
       
    ; Per CPU Config
    ; r10 = IC_INT_BASE
    ;;; --------------------------------
    ;;; -Interrupt Priority Mask (ICCPMR)
    ;;; --------------------------------
    [ :DEF:VERBOSE
       MESSAGE "Interrupt Priority Mask register\n"
    ]
       LDR  r1,[r10, #0x04]
       CMP   r1, #0
       BNE   fail
       MOV   r1, #0xf8 ; set priority reg to allow all priority levels to reach CPU
       STR   r1, [r10, #0x04]

       ; MESSAGE "Check2\n"
       
    ;;; --------------------------------
    ;;; -Interrupt Binary Point (ICCBPR)
    ;;; --------------------------------
    [ :DEF:VERBOSE
        MESSAGE "Binary Point register\n"
    ]
        MOV  r1, #3
        STR  r1, [r10, #0x08]

        ;MESSAGE "Check3\n"
       
    ;;; --------------------------------
    ;;; -Interface Control Register (ICCICR)
    ;;; --------------------------------
    [ :DEF:VERBOSE
        MESSAGE "CPU Interface Control Register\n"
    ]
        MOV  r1, #0x1f  ;enable the interface
        STR  r1, [r10]
        ;Enable the Interrupt Interface disables legacy nFIQ/nIRQ support.
        ;The nFIQ/nIRQ pins then become part of the IRQS bus input pins to the controller.


    ;;; --------------------------------
    ;;; -Distributor Control Register (ICDDCR)
    ;;; --------------------------------
    [ :DEF:VERBOSE
            MESSAGE "Distributor Control register\n"
    ]
        ; Now we need to enable the intterupts
        ; The IRQS[] pins won't do anything without being enabled in the distributor
        MOV  r1, #0x1  ; enable SPI/PPI for Secure and Non-Secure modes
        STR  r1, [r11]

     
    Please let me know if I am missing something.

    Thanks
    Lokesh
Reply
  • Note: This was originally posted on 5th September 2012 at http://forums.arm.com

    Hi ttfn,

    Yes you are right I am using cortex A9 MP core
    Here is what I am configuring
      ;;; --------------------------------
    ;;; -Interrupt Security (ICDISR) (ICDISR0 is banked per processor)
    ;;; --------------------------------
        ; Define the security for this SPI interrupt
    [ :DEF:VERBOSE
        MESSAGE "Setting Interrupt Security\n"
    ]
        LDR  r2, =0x00000000 ; 1 = non-secure, 0 = secure
        ADD  r3, r11, #0x80
        MOV  r0, #0
    int_secure_loop
        STR  r2, [r3]
        ADD  r0, r0, #0x1
        ADD  r3, r3, #0x4
    ;    CMP  r0, #0x08 ;#NUM_INT_LOOPS  ;only need 8 times
        CMP  r0, #NUM_INT_LOOPS 
        BNE   int_secure_loop
    ;;; --------------------------------
    ;;; -Interrupt Edge Trigger Config (ICDIFR)
    ;;; --------------------------------
    [ :DEF:VERBOSE
        MESSAGE "Setting Interrupt Trigger Cfg\n"
    ]
        LDR  r2, =0xffffffff ; 1 = edge, 0 = level
        ADD  r3, r11, #0xc00
        MOV  r0, #0
    int_edge_cfg_loop
        STR  r2, [r3]
        ADD  r0, r0, #0x1
        ADD  r3, r3, #0x4
    ;    CMP  r0, #0x10 ;#NUM_INT_LOOPS
        CMP  r0, #NUM_INT_LOOPS
        BNE   int_edge_cfg_loop

    ;;; --------------------------------
    ;;; -Interrupt Priority (ICDIPR)
    ;;; --------------------------------
    [ :DEF:VERBOSE
        MESSAGE "Set Priority (greater than 0 to avoid masking)\n"
    ]
        ADD  r3, r11, #0x400
        LDR  r1, =0x08080808 ;; just make all priorities the same for this test
        MOV  r0, #0
    set_pri_loop   
    ;    STR  r1, [r3, #0x4]
        STR  r1, [r3]
        ADD  r0, r0, #0x1
        ADD  r3, r3, #0x4
        CMP  r0, #NUM_INT_LOOPS
        BNE   set_pri_loop
       
    ;;; --------------------------------
    ;;; -Interrupt Target Processor (ICDIPTR)
    ;;; --------------------------------
        ; Define the target for this SPI interrupt
    [ :DEF:VERBOSE
        MESSAGE "Setting Interrupt Targets\n"
    ]
    ; --- For example purposes, we'll have one processor as an individual target per interrupt
        LDR  r2, =0x01010101 ; See GIC Arch spec : one byte per interrupt : 1 = CPU0, 2 = CPU1, 4=CPU2, 8=CPU3
        ADD  r3, r11, #0x800
        MOV  r0, #0
    int_target_loop
        STR  r2, [r3, #32] ;; Int ID's 0-31 are banked per CPU and not programmed for target processors
        ADD  r0, r0, #0x1
        ADD  r3, r3, #0x4
        CMP  r0, #NUM_INT_LOOPS
        BNE   int_target_loop

    ;;; --------------i------------------
    ;;; -Interrupt Enable (ICDISER)
    ;;; --------------------------------
        ; Now we need to enable the intterupts
    [ :DEF:VERBOSE
        MESSAGE "Enable Interrupts\n"
    ]
        LDR  r2, =0xffffffff
        ADD  r3, r11, #0x100
        MOV  r0, #0
    set_enable_loop
    ;    STR  r2, [r3, #0x4]
        STR  r2, [r3]
        ADD  r0, r0, #0x1
        ADD  r3, r3, #0x4
    ;    CMP  r0, #0x4 ;#NUM_INT_LOOPS
        CMP  r0, #NUM_INT_LOOPS
        BNE   set_enable_loop
       
    ; Per CPU Config
    ; r10 = IC_INT_BASE
    ;;; --------------------------------
    ;;; -Interrupt Priority Mask (ICCPMR)
    ;;; --------------------------------
    [ :DEF:VERBOSE
       MESSAGE "Interrupt Priority Mask register\n"
    ]
       LDR  r1,[r10, #0x04]
       CMP   r1, #0
       BNE   fail
       MOV   r1, #0xf8 ; set priority reg to allow all priority levels to reach CPU
       STR   r1, [r10, #0x04]

       ; MESSAGE "Check2\n"
       
    ;;; --------------------------------
    ;;; -Interrupt Binary Point (ICCBPR)
    ;;; --------------------------------
    [ :DEF:VERBOSE
        MESSAGE "Binary Point register\n"
    ]
        MOV  r1, #3
        STR  r1, [r10, #0x08]

        ;MESSAGE "Check3\n"
       
    ;;; --------------------------------
    ;;; -Interface Control Register (ICCICR)
    ;;; --------------------------------
    [ :DEF:VERBOSE
        MESSAGE "CPU Interface Control Register\n"
    ]
        MOV  r1, #0x1f  ;enable the interface
        STR  r1, [r10]
        ;Enable the Interrupt Interface disables legacy nFIQ/nIRQ support.
        ;The nFIQ/nIRQ pins then become part of the IRQS bus input pins to the controller.


    ;;; --------------------------------
    ;;; -Distributor Control Register (ICDDCR)
    ;;; --------------------------------
    [ :DEF:VERBOSE
            MESSAGE "Distributor Control register\n"
    ]
        ; Now we need to enable the intterupts
        ; The IRQS[] pins won't do anything without being enabled in the distributor
        MOV  r1, #0x1  ; enable SPI/PPI for Secure and Non-Secure modes
        STR  r1, [r11]

     
    Please let me know if I am missing something.

    Thanks
    Lokesh
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