• Locked Locked
  • Replies 9 replies
  • Subscribers 118 subscribers
  • Views 5429 views
  • Users 0 members are here
Options
Related
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

Assertion of IRQS is not causing calling of ISR

Lokesh Kumar
Note: This was originally posted on 4th September 2012 at http://forums.arm.com

Hi,

With my current flow, when I am asserting legacy nIRQ I am able to jump to ISR, but not when asserting IRQS[0].
I have enabled interrupts as below
[size=2]CPSIE   ifa, #18

and configured [size=2]Interrupt Security ([/size][/size][size=2][size=2]ICDISR), [size=2][/size][/size][/size][size=2][size=2][size=2][size=2]Interrupt Edge Trigger Config ([/size]ICDIF),[size=2]Interrupt Priority (ICDIPR)[/size][/size][/size][/size],[size=2]Interrupt Target Processor (ICDIPTR),[size=2]Interrupt Enable (ICDISER),[size=2]Interrupt Priority Mask (ICCPMR),[size=2]Interrupt Binary Point (ICCBPR),[size=2]Interface Control Register (ICCICR),[size=2]Distributor Control Register (ICDDCR)

Am I missing something?
Is something separate need to be done, when using IRQS interrupts?

Thanks
Lokesh
[/size][/size][/size][/size][/size][/size]
Parents
  • Note: This was originally posted on 6th September 2012 at http://forums.arm.com

    Yes I have cleared it by following instruction

    CPSIE   ifa, #18

    Which GIC spec you are referring.
    I was going through IHI0048A_gic_architecture_spec_v1_0.pdf, but when I searched it on arm infocenter looks like second version of spec is available.
    As per version 2
    [0] EnableGrp1
    [4:1] - Reserved
    [5] FIQBypDisGrp1
    [6] IRQBypDisGrp1
    [8:7] - Reserved.
    [9] EOImodeNS

    So writing 0x1f also may not affect FIQ.
    Anyway which document will be used for cortex A9 mp core.


Reply
  • Note: This was originally posted on 6th September 2012 at http://forums.arm.com

    Yes I have cleared it by following instruction

    CPSIE   ifa, #18

    Which GIC spec you are referring.
    I was going through IHI0048A_gic_architecture_spec_v1_0.pdf, but when I searched it on arm infocenter looks like second version of spec is available.
    As per version 2
    [0] EnableGrp1
    [4:1] - Reserved
    [5] FIQBypDisGrp1
    [6] IRQBypDisGrp1
    [8:7] - Reserved.
    [9] EOImodeNS

    So writing 0x1f also may not affect FIQ.
    Anyway which document will be used for cortex A9 mp core.


Children
No data