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Assertion of IRQS is not causing calling of ISR

Lokesh Kumar
Note: This was originally posted on 4th September 2012 at http://forums.arm.com

Hi,

With my current flow, when I am asserting legacy nIRQ I am able to jump to ISR, but not when asserting IRQS[0].
I have enabled interrupts as below
[size=2]CPSIE   ifa, #18

and configured [size=2]Interrupt Security ([/size][/size][size=2][size=2]ICDISR), [size=2][/size][/size][/size][size=2][size=2][size=2][size=2]Interrupt Edge Trigger Config ([/size]ICDIF),[size=2]Interrupt Priority (ICDIPR)[/size][/size][/size][/size],[size=2]Interrupt Target Processor (ICDIPTR),[size=2]Interrupt Enable (ICDISER),[size=2]Interrupt Priority Mask (ICCPMR),[size=2]Interrupt Binary Point (ICCBPR),[size=2]Interface Control Register (ICCICR),[size=2]Distributor Control Register (ICDDCR)

Am I missing something?
Is something separate need to be done, when using IRQS interrupts?

Thanks
Lokesh
[/size][/size][/size][/size][/size][/size]
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  • Note: This was originally posted on 4th September 2012 at http://forums.arm.com

    ttfn,

    Is that vector address will be different for IRQS[0] compared to nIRQ?

    If so what is logic to derive vector address for IRQS[0].. IRQS[n]?

    For nIRQ as suggested I am using base address + 0x18

    VecTable
                 LDR  pc, [pc,#0x18]


    Is this same same for all IRQ or different for different IRQS?
Reply
  • Note: This was originally posted on 4th September 2012 at http://forums.arm.com

    ttfn,

    Is that vector address will be different for IRQS[0] compared to nIRQ?

    If so what is logic to derive vector address for IRQS[0].. IRQS[n]?

    For nIRQ as suggested I am using base address + 0x18

    VecTable
                 LDR  pc, [pc,#0x18]


    Is this same same for all IRQ or different for different IRQS?
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