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Relationship between ready and valid signals

quy truong
Note: This was originally posted on 14th August 2012 at http://forums.arm.com

Hi there,
I am wondering about the relationship between rready and rvalid signals (or wready and wvalid signals). when I do a burst write operation (or burst read) with burst length of 4 transfers, I mean that the wvalid (or rvalid) signals must be asserted in at least 4 clock cycles from when write data (or read data) is available on the data bus, but I don't sure about whether wready (or rready) signal must be asserted at least 4 clock cycles (based burst length) or not to make the transmission of 4 transfers in burst operation. Can you help me for explaining it?
Many thanks.
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