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GIC Acknowledge Register read has no impact

Sebastian Meisheit
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Note: This was originally posted on 30th July 2012 at http://forums.arm.com

Hi,

Setup:
I am using Pandaboard ES with Cortex-A9MP (2x Cortex-A9) and connect to processor_0 by JTAG and Lauterbach hardware debugger.
From GICD_TYPER [10] = 1 i know the GIC implements Security Extensions.
From the Peripheral ID2 Register [7:4] = 1 i know its GICv1.
I am not able to enter Secure World (SMC or CPSR mode change doesnt work on the PandaES), so every access would be non-secure.

Problem:
According to the ICCIAR definition, an interrupt pending on a CPU interface should change from pending to active only after the register ICCIAR is read. In my GIC the interrupt changes immediately to active, if the priority is sufficient. I use the ICCIAR to get the current interrupt ID, but it has no efffect on the CPU interface or the GIC registers.
Is the ICCIAR definition wrong here, or am i missing something?

Greets
Sebastian
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    Note: This was originally posted on 31st July 2012 at http://forums.arm.com

    You're correct that interrupts go from Pending to Active by reading the Ack register (GICC_AIR).

    NOTE... In GICv2 (i.e. A15/A7 orGIC-400) you can force an interrupt to the Active state by writing to the GICD_ISACTIVER, but that doesn't apply here. :-)

    Couple of thoughts... the mostly likely to my mind is that one of the other cores is acknowledging the interrupt.  You said that you're connected to CPU0, what is CPU1 doing?

    Other thought... the Secure world code could be acknowledging the interrupt.  This seems less likely as usually the Secure world code only handles secure interrupts - which you Normal world code would never get to see.
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    Note: This was originally posted on 31st July 2012 at http://forums.arm.com

    You're correct that interrupts go from Pending to Active by reading the Ack register (GICC_AIR).

    NOTE... In GICv2 (i.e. A15/A7 orGIC-400) you can force an interrupt to the Active state by writing to the GICD_ISACTIVER, but that doesn't apply here. :-)

    Couple of thoughts... the mostly likely to my mind is that one of the other cores is acknowledging the interrupt.  You said that you're connected to CPU0, what is CPU1 doing?

    Other thought... the Secure world code could be acknowledging the interrupt.  This seems less likely as usually the Secure world code only handles secure interrupts - which you Normal world code would never get to see.
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