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Cortex-A9 CPSR I Flag unmask problem

Sebastian Meisheit
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  • Arm Employee Badge
    Note: This was originally posted on 18th July 2012 at http://forums.arm.com

    Just sanity checking....  "CPSID i" will set the CPSR.I bit which disables (not enables) interrupts.  Is that what you meant?

    Have you checked what address is in the LR_abt and pattern in SPSR_abt?  If it is a data abort you probably also want to check the CP15 DFSR and DFAR.

    Best guess... the "CPSIE i" succeeds and an IRQ is immediately taken.  The IRQ handler triggers an Abort - hence ending up in abort mode. 

    NOTE: Taking any exception will cause the CPSR.I bit to be set.  So if an abort or IRQ is being taken, it would be expected that the CPSR.I bit gets set again.
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  • Arm Employee Badge
    Note: This was originally posted on 18th July 2012 at http://forums.arm.com

    Just sanity checking....  "CPSID i" will set the CPSR.I bit which disables (not enables) interrupts.  Is that what you meant?

    Have you checked what address is in the LR_abt and pattern in SPSR_abt?  If it is a data abort you probably also want to check the CP15 DFSR and DFAR.

    Best guess... the "CPSIE i" succeeds and an IRQ is immediately taken.  The IRQ handler triggers an Abort - hence ending up in abort mode. 

    NOTE: Taking any exception will cause the CPSR.I bit to be set.  So if an abort or IRQ is being taken, it would be expected that the CPSR.I bit gets set again.
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