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Why nested interrupt corrupt Link Register?

Harri Wijaya
Note: This was originally posted on 13th June 2012 at http://forums.arm.com

hi,
Sorry for this basic question.

I find hard to understand why the Link Register can be corrupted in this below scenario:
1. IRQ interrupt occur.
2. IRQ ISR call a function foo(). (assume inside ISR, the IRQ interrupt is reenabled)
3. foo() is interrupted by another IRQ interrupt.

From what I understand:

*During (1):

STACK content:
some general purpose registers
LR_irq_1 (let call like that to indicate that the content is point to address of interrupted function by scenario-1)

LR_irq = address-1 (see LR_irq_1)

*During (2):

STACK content:
some general purpose registers
LR_irq_2
some general purpose registers
LR_irq_1

LR_irq = address-2 (address of a line within ISR)

*During (3):

STACK content:
some general purpose registers
LR_irq_3
some general purpose registers
LR_irq_2
some general purpose registers
LR_irq_1

LR_irq = address-3 (address of a line within foo() where second IRQ interrupt occur)


Assuming that we have enough IRQ stack size, then from above context, seem no reason for LR to be corrupted.

Any body could help me explain what causing LR to be corrupted?

Thanks!
Parents
  • Arm Employee Badge
    Note: This was originally posted on 14th June 2012 at http://forums.arm.com

    Once IRQs have been reenabled in IRQ mode there is a possibility of LR corruption even if the callee saves/restores LR.  Consider the case where the processor is executing 'BL bar2' when the IRQ is signalled.  The current instruction (the BL) will be completed and will store the return address in LR and set the PC to bar2.  But before the first instruction of bar2 can execute, the IRQ will be handled and overwrite/corrupt LR (game over).

    Another corruption possibility is that in a function like your foo, once the initial value of LR has been stacked the compiler may use LR as a temporary register (with the understanding that BL will use/corrupt LR).  If the compiler is using LR as a temporary when an IRQ is handled, similar problems will result.
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  • Arm Employee Badge
    Note: This was originally posted on 14th June 2012 at http://forums.arm.com

    Once IRQs have been reenabled in IRQ mode there is a possibility of LR corruption even if the callee saves/restores LR.  Consider the case where the processor is executing 'BL bar2' when the IRQ is signalled.  The current instruction (the BL) will be completed and will store the return address in LR and set the PC to bar2.  But before the first instruction of bar2 can execute, the IRQ will be handled and overwrite/corrupt LR (game over).

    Another corruption possibility is that in a function like your foo, once the initial value of LR has been stacked the compiler may use LR as a temporary register (with the understanding that BL will use/corrupt LR).  If the compiler is using LR as a temporary when an IRQ is handled, similar problems will result.
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