• Locked Locked
  • Replies 3 replies
  • Subscribers 119 subscribers
  • Views 5086 views
  • Users 0 members are here
2025 survey

We are running a survey to help us improve the experience for all of our members. If you see the survey appear, please take the time to tell us about your experience if you can.

Options
Related
How was your experience today?
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

Pin Interrupt Enable/Disable Confusion

thomas ketnawang
Note: This was originally posted on 11th June 2012 at http://forums.arm.com

Hello, at the moment i study the LPC11U1x manual(Cortex-M0) and i found some very confusing thing, in the GPIO interrupt registers to enable a rising edge or level interrupt i can set a bit in IENR or delete a bit to disable the interrupt. but the CIENR disables a interrupt by deleting the corresponding  bit in IENR and again there is SIENR that only set the corresponding bit in IENR

ISEL Pin Interrupt Mode register: Selects if edge or level sensitive

IENR Pin Interrupt Enable: Enables rising edge/level interrupt
0 = Disable rising edge or level interrupt.
1 = Enable rising edge or level interrupt

SIENR Set Pin Interrupt Enable
0 = No operation.
1 = Enable rising edge or level interrupt.

CIENR Clear Pin Interrupt Enable
0 = No operation.
1 = Disable rising edge or level interrupt.

IST Pin Interrupt Status register
1 =  (edge-sensitive): clear rising- and falling-edge detection for this pin.

So if i have a rising edge interrupt i can set him over IENR or SIENR
if i wont to disable the interrupt i can do that by IENR or CIENR or IST
so IST my make sense but why CIENR and SIENR

is this for compatibility with other cortex`s?.  did i understood it right?

Regards Thomas
Parents Reply Children
No data