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Cortex-M3 Branch instruction encoding?

Chris Burrows
Note: This was originally posted on 11th June 2012 at http://forums.arm.com

In the process of implementing the Cortex-M3 code generator for our Astrobe Oberon compiler I was unable to find a definition for the calculation of 'imm32'  in the T3 Encoding version of the 32-bit conditional branch instruction (see Section A7.7.12 of ARMv7-M Architecture Reference Manual, ARM DDI 0403D)

Experiments indicate that the J1 and J2 bits are not used and the definition is:

imm32 = SignExtend(S:imm6:imm11:'0', 32);

Is that correct?
Parents
  • Note: This was originally posted on 11th June 2012 at http://forums.arm.com

    Yes - you are right. I Googled your version of the statement and found that it was actually present in earlier revisions of the manual.

    Also, with the benefit of hindsight, the note in the latest manual that the range of allowed offsets for encoding T3 is -1048576 to 1048574 clearly shows that it must be a 21-bit number so the J1 and J2 bits must be used.

    Thank you very much for helping to solve that puzzle for me,

    Chris.
Reply
  • Note: This was originally posted on 11th June 2012 at http://forums.arm.com

    Yes - you are right. I Googled your version of the statement and found that it was actually present in earlier revisions of the manual.

    Also, with the benefit of hindsight, the note in the latest manual that the range of allowed offsets for encoding T3 is -1048576 to 1048574 clearly shows that it must be a 21-bit number so the J1 and J2 bits must be used.

    Thank you very much for helping to solve that puzzle for me,

    Chris.
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