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Cortex-M3 Branch instruction encoding?

Note: This was originally posted on 11th June 2012 at http://forums.arm.com

In the process of implementing the Cortex-M3 code generator for our Astrobe Oberon compiler I was unable to find a definition for the calculation of 'imm32' in the T3 Encoding version of the 32-bit conditional branch instruction (see Section A7.7.12 of ARMv7-M Architecture Reference Manual, ARM DDI 0403D)

Experiments indicate that the J1 and J2 bits are not used and the definition is:

imm32 = SignExtend(S:imm6:imm11:'0', 32);

Is that correct?

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Simon Craske over 12 years ago

Note: This was originally posted on 11th June 2012 at http://forums.arm.com

I believe it's meant to be: imm32 = SignExtend(S:J2:J1:imm6:imm11:'0', 32);

hth
s.
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Simon Craske over 12 years ago

Note: This was originally posted on 11th June 2012 at http://forums.arm.com

I believe it's meant to be: imm32 = SignExtend(S:J2:J1:imm6:imm11:'0', 32);

hth
s.
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