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Cortex-A5 NEON issue

Jason Martin
Note: This was originally posted on 2nd June 2012 at http://forums.arm.com

In attempting to use the NEON core on the Cortex-A5, I've encountered issues with the VST instruction. This seems to be reproducible when using the upper q registers(8-15).

The following code was tested:
[size="2"]vmov.64 q11, 0x1000000001[/size]
[size="2"]vadd.i32 q12, q8, q11[/size]
[size="2"]vadd.i32 q13, q9, q11[/size]
[size="2"]vst4.32 {d24, d25, d26, d27}, [r1]![/size]
[size="2"]vst4.32 {d16, d17, d18, d19}, [r1]![/size]
[size="2"]vst1.32 {d22}, [r1][/size]

[size="2"]r1 points to an address in RAM. [/size]
[size="2"] [/size]
[size="2"]When q8 - q13 registers are used, the value being stored by the vst4.32 are incorrect. When using q0-q4, the values are always correct. When using a combination of q0-q4 with q8-q13, the issue is also present and bad values are being stored. These instructions worked fine on the Cortex-A8 with NEON. Is there a difference here that I'm not understanding? [/size] [size="2"]Are there limitations using registers > d16? And I believe it's also true that the Cortex-A5 uses the vfpv4? Which is D32, not vfpv3-D16. [/size] Thanks     
  • Arm Employee Badge
    Note: This was originally posted on 7th June 2012 at http://forums.arm.com

    The Cortex-A5 has a configurable MPE / FPU option, it supports the following:

    None
    VFPv4-D16
    VFPv4 and NEON


    The configuration of the Cortex-A5 will be implementation specific, what device are you using?
    It may be that you only have the VFPv4-D16 configuration in your implementation.
  • Arm Employee Badge
    Note: This was originally posted on 7th June 2012 at http://forums.arm.com

    After re-reading your post I see that if you did not have the VFPv4 + NEON configuration then the code would fault. I assume no faults are generated, but the stored data is corrupt?It would be useful if you could show what exactly is in them registers and the corresponding stored data in memory?