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LL/SC exclusive access by register width or cache line width?

Toebs Douglass
Note: This was originally posted on 30th May 2012 at http://forums.arm.com

Hi.

I'm working on the next release of my lock-free data structure library.

I'm using LL/SC on ARM.

To use LL/SC as LL/SC (rather than emulating CAS) there has to be a single STR between the LDREX and STREX.

Now, I've written the code and this works.

What concerns me however is the possibility it may not work.

I've read on PowerPC if you access the same cache line as the LL/SC target, you break the LL/SC.

So I'm thinking if my STR target is on the same cache line as my LL/SC target, then pow, I'm dead.

Now, the LL/SC target and STR targets are always in different malloc()s so the chance of them being directly in the same cache line is probably small (and I can guarantee this by padding the LL/SC target so it begins on a cache line boundary and fills that cache line).

But there coud be false sharing, if the STR target is in just the right (wrong!) place in memory.

Looking at the LDREX/STREX documentation, this descriibes exclusive access in terms of "the physical address".  This implies register width granularity, not cache line width granularity.

And that's my question - is LDREX/STREX sensitivity to memory access using register width granularity or cache line width granularity?
Parents
  • Note: This was originally posted on 31st May 2012 at http://forums.arm.com

    > > I've been told in StackOverflow the block size ranges from 8 to 2048 bytes.

    > On some of the older uni-processor ARM11 cores (e.g. ARM1176) which don't have SMP support there is no address tracking at all; the local monitor is just a single bit which is
    > either 1 or 0 (set by LDREX, cleared by STREX or CLREX, STREX fails if the bit is zero). So the logical block size is 4GB in these cases. That said I think this design allows
    > "other stores" to land in-between the LDREX and the STREX, so you'll probably get away with it ;P
    Erk!

    Hmm.  Actually, in the unit test for the abstraction layer I can probe the block size by doing a malloc and trying LL/STR/SC with the STR being varying distances from the LL/SC target.

    When people run the test on their target platform they'll know then if it works or not.
Reply
  • Note: This was originally posted on 31st May 2012 at http://forums.arm.com

    > > I've been told in StackOverflow the block size ranges from 8 to 2048 bytes.

    > On some of the older uni-processor ARM11 cores (e.g. ARM1176) which don't have SMP support there is no address tracking at all; the local monitor is just a single bit which is
    > either 1 or 0 (set by LDREX, cleared by STREX or CLREX, STREX fails if the bit is zero). So the logical block size is 4GB in these cases. That said I think this design allows
    > "other stores" to land in-between the LDREX and the STREX, so you'll probably get away with it ;P
    Erk!

    Hmm.  Actually, in the unit test for the abstraction layer I can probe the block size by doing a malloc and trying LL/STR/SC with the STR being varying distances from the LL/SC target.

    When people run the test on their target platform they'll know then if it works or not.
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