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Unable to trigger SWI via GIC on Cortex A15

Wallace Wadge
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  • Arm Employee Badge
    Note: This was originally posted on 17th April 2012 at http://forums.arm.com

    Have you cleared the CPSR.I bit?  This is the bit which masks interrupts (IRQs) in the CPU, and is set (IRQs masked) at reset.  So you would need to clear it. 

    Other possibility, the code you quoted - is it running in the Secure world or Normal world (SCR.NS bit state)?  If Normal world, you need to perform some steps in the Secure world before you can use the IC in the Normal world.
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  • Arm Employee Badge
    Note: This was originally posted on 17th April 2012 at http://forums.arm.com

    Have you cleared the CPSR.I bit?  This is the bit which masks interrupts (IRQs) in the CPU, and is set (IRQs masked) at reset.  So you would need to clear it. 

    Other possibility, the code you quoted - is it running in the Secure world or Normal world (SCR.NS bit state)?  If Normal world, you need to perform some steps in the Secure world before you can use the IC in the Normal world.
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