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GIC IAR always returns spurious interrupt

Steve Jahr
Note: This was originally posted on 29th March 2012 at http://forums.arm.com

Trying to write a GIC driver (V1 w/security extensions) on an embedded A9 MPCORE based system with 2 cores.

Can successfully initialize GIC and issue SGI interrupt from each CPU to the other CPU.
These interrupts show up on each side in pending state.
IRQ posted to CPU, CPU responds and reads IAR getting 0x3ff response.
GIC changes state of interrupt from pending to active.
GIC adjusts running priority to priority of active interrupt.

I have verified that CPUs are running in secure mode and all interrupts are configured in secure mode.
I have compared my code with the ARM ukernel reference code and can find no material differences (I have changed mine to more closely match all options).

What am I missing here?  How is it that the GIC seems to believe a valid interrupt acknowledge has occurred (as indicated by change of interrupt state) but not return valid interrupt ID to IAR read?
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  • Note: This was originally posted on 31st March 2012 at http://forums.arm.com

    This is kinda kludgey and not a real solution but as a workaround it seems to work:

    Rather than reading the interrupt ID from the IAR instead read it from the HPPIR.  Prior to acknowledging the interrupt via an IAR read it should be in the HPPIR anyways.  If it is not the spurious interrupt ID, then read the IAR and toss the results using the HPPIR value instead.

    There is one additional niggling detail... the HPPIR is not priority masked so you also have to model the GIC priority mask logic in S/W logic to fully determine that the HPPIR interrupt ID is valid.

    So everything in my driver is working *except* for the one line:
         intID = gicCpu->GICC_IAR;

    And even that halfway works as it advances the interrupt state machine from the pending state to the active state while returning interrupt ID 0x3ff.
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  • Note: This was originally posted on 31st March 2012 at http://forums.arm.com

    This is kinda kludgey and not a real solution but as a workaround it seems to work:

    Rather than reading the interrupt ID from the IAR instead read it from the HPPIR.  Prior to acknowledging the interrupt via an IAR read it should be in the HPPIR anyways.  If it is not the spurious interrupt ID, then read the IAR and toss the results using the HPPIR value instead.

    There is one additional niggling detail... the HPPIR is not priority masked so you also have to model the GIC priority mask logic in S/W logic to fully determine that the HPPIR interrupt ID is valid.

    So everything in my driver is working *except* for the one line:
         intID = gicCpu->GICC_IAR;

    And even that halfway works as it advances the interrupt state machine from the pending state to the active state while returning interrupt ID 0x3ff.
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