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Weird interrupt behaviour on Cortex-A8

Jitesh Shah
Note: This was originally posted on 4th April 2012 at http://forums.arm.com

My current configuration is as follows:
Cortex A8 with TrustZone enabled. I have both secure and normal world running. Monitor mode is setup and is working neatly. All exception tables are in place.
FIQs are configured to be trapped in the monitor mode (Bit 2 in Secure Configuration Register - c1, c1, 0, 0 in cp15)

Both IRQ and FIQ are enabled in secure as well as normal world. All interrupts are IRQs except a timer interrupt. Expectation is that, periodically the timer will trigger and trap into the monitor mode.

Now, when I am in the secure world, this works fine. The timer triggers, the hardware is trapped into the monitor mode and the FIQ vector is executed. However, if I am executing in the normal world, the timer interrupt *never* occurs. I haven't done any special setting in the normal world and I don't reckon its required. My expectation was that, irrespective of which world is being executed, the control will go into the monitor mode.

Is my understanding wrong? Shouldn't the hardware trap me into monitor mode from the normal world if the timer interrupt occurs with the above described settings?

Thanks,
Jitesh
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  • Note: This was originally posted on 5th April 2012 at http://forums.arm.com

    Hi Mallikarjun,
    Thanks for the reply.

    Please make sure, you are verifying it in the FIQ expcetion handler of Monitor mode. The  Vector table for the Monitor mode is different.
    MVBAR holds the exception base address for the Monitor mode.


    The MVBAR has been properly initialized. I am using the smc instruction to switch between the world. smc uses the monitor vector table, so I am sure that MVBAR is initialized properly.



    Also make sure whether you have enabled Vectored Interrupt bit or not. If SCTLR.VE is 1, then the FIQ exception handler is implementation defined.


    I have explicitly disabled the vectored interrupt support, since I won't be using it at all. So, SCTLR.VE is turned off in both secure as well as non-secure modes.

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  • Note: This was originally posted on 5th April 2012 at http://forums.arm.com

    Hi Mallikarjun,
    Thanks for the reply.

    Please make sure, you are verifying it in the FIQ expcetion handler of Monitor mode. The  Vector table for the Monitor mode is different.
    MVBAR holds the exception base address for the Monitor mode.


    The MVBAR has been properly initialized. I am using the smc instruction to switch between the world. smc uses the monitor vector table, so I am sure that MVBAR is initialized properly.



    Also make sure whether you have enabled Vectored Interrupt bit or not. If SCTLR.VE is 1, then the FIQ exception handler is implementation defined.


    I have explicitly disabled the vectored interrupt support, since I won't be using it at all. So, SCTLR.VE is turned off in both secure as well as non-secure modes.

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