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Setting 'shareable' attribute in PT entry discard cache policies ?

Sujith K V
Note: This was originally posted on 21st March 2012 at http://forums.arm.com

Hi,

I am working on Cortex-A8 with MMU Enabled.

I am configuring L1 as Write Through No Write Allocate and L2 as Write Back Write Allocate. Both L1 and L2 caches are enabled.

And the memory attribute is given normal memory and  'shareable'  in the page table entry.

Then, When I write to a variable, its also written to memory.

When I change only the memory attribute to 'non-shareable', the variable is written to cache only.

Is shareability attribute means, irrespective of the cache attributes we set, it will be 'write through ??', Or all writes are happening to memory only?

I dont see any other CP15 register settings which can cause this behaviour.

Can anyone help me ?

Regards,




  • Note: This was originally posted on 22nd March 2012 at http://forums.arm.com

    Thank you very much for replying to this query!

    so I understand from your reply, that the implementation of the SoC might be making the Memory and Cache coherent if  the region is marked 'Shared'.

    But doesnt it reduce the perfomance, if I mark it shareable, since this coherency needs to be maintained? also, in ARM ARM, i couldnt find anywhere this mentioned. :(

    Regards
  • Note: This was originally posted on 21st March 2012 at http://forums.arm.com

    In general, cache policies are defined in the ARM ARM as "wishful thinking". The processor implementation may ignore them under certain conditions.
    Declaring a region as non-shareable means that no other master in the system will access that region. From the processor core's perspective it makes no difference whether the actual cache behavior is write-through (as configured) or write back.

    Kind regards
    Marcus
  • Note: This was originally posted on 23rd March 2012 at http://forums.arm.com


    so I understand from your reply, that the implementation of the SoC might be making the Memory and Cache coherent if  the region is marked 'Shared'.

    Please have a look at the relevant sections in the ARM ARM for details.


    But doesnt it reduce the perfomance, if I mark it shareable, since this coherency needs to be maintained?

    In a single core system all it takes are write-through or NC accesses. In most cases this does indeed limit performance, which is why  you should think hard about which memory regions absolutely have to be shareable. It may (or may not) be better to leave coherency management to higher level software using explicit cache maintenance operations.

    --
    Marcus