Dear All,As I know, In Cortex M3, was implemented such as the B_ROM, I_RAM, D_RAM .and Basically, Cortex M3 is consist with internal memory ROM and SRAM.In Boot sequence, first of all, IROM code load BL1 code into the SRAM.So I want to know especially How do I make IROM code. I can't find ROM example.Would you please let me know such as any example (code) or documents..?How do I implement the cortex M3 Boot ROM code?
Yes, flash access latency is usually much higher than SRAM.
However,
- you don't write to flash in normal operations. You still use SRAM for R/W data (e.g. local variables, stack, heap, etc).
- with AHB flash cache the access latency is mostly avoided (except when cache missed).
For the same memory size, the area of SRAM is larger than flash, which means higher silicon cost. So execute directly from flash (with caching) is best for most microcontroller applications.
regards,
Joseph