In AXI Interface, is the VALID signal of the master dependent on the slave's READY signal

Hi,

I am seeing an issue, where the READY signal's assertion depends on the VALID signal. If the VALID signal remains asserted through out the transaction (Say, for a burst transfer), then for the second burst beat to occur, the WREADY should have been asserted by slave, but didn't assert, as the VALID is high.

Can you confirm, whether VALID signal should be dependent on the READY signal.

Thanks.